Demonstration of Low-Power Three-Dimensional CMOS Inverters based on Si p-Tunnel FET and ITO n-FET
In this work, low-power CMOS inverter and 5-stage ring oscillator (RO) are demonstrated based on heterogeneous 3D integration of vertically stacked FEOL p-type silicon tunnel FET (TFET) and BEOL n-type indium-tin-oxide (ITO) FET. Owing to the low off-state current of both p-type and n-type FET, our...
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| Veröffentlicht in: | IEEE electron device letters 2025-01, p.1-1 |
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| creator | Tong, Anyu Wang, Kaifeng Hu, Qianlan Wang, Zhiyu Xiong, Xiong Yan, Shiwei Zhu, Shenwu Li, Qijun Wu, Yongqin Ren, Ye Bu, Weihai Huang, Qianqian Wu, Yanqing Huang, Ru |
| description | In this work, low-power CMOS inverter and 5-stage ring oscillator (RO) are demonstrated based on heterogeneous 3D integration of vertically stacked FEOL p-type silicon tunnel FET (TFET) and BEOL n-type indium-tin-oxide (ITO) FET. Owing to the low off-state current of both p-type and n-type FET, our ITO/TFET heterogeneous 3D integrated CMOS inverters show a low static power of 4.83 pW at V dd = 1 V and a high voltage gain of 522 V/V at V dd = 2.5 V, among the best values in reported amorphous oxide semiconductors (AOS) CMOS devices. Meanwhile, we also verified the functionality of logic circuits including 4T-SRAM cell and 5-stage RO based on our ITO/TFET heterogeneous 3D integrated CMOS inverters, and our 5-stage RO achieved a low propagation delay of 30 ns/stage, which is also the lowest value among AOS and TFET related CMOS devices. |
| doi_str_mv | 10.1109/LED.2025.3528045 |
| format | Article |
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Owing to the low off-state current of both p-type and n-type FET, our ITO/TFET heterogeneous 3D integrated CMOS inverters show a low static power of 4.83 pW at V dd = 1 V and a high voltage gain of 522 V/V at V dd = 2.5 V, among the best values in reported amorphous oxide semiconductors (AOS) CMOS devices. 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Owing to the low off-state current of both p-type and n-type FET, our ITO/TFET heterogeneous 3D integrated CMOS inverters show a low static power of 4.83 pW at V dd = 1 V and a high voltage gain of 522 V/V at V dd = 2.5 V, among the best values in reported amorphous oxide semiconductors (AOS) CMOS devices. Meanwhile, we also verified the functionality of logic circuits including 4T-SRAM cell and 5-stage RO based on our ITO/TFET heterogeneous 3D integrated CMOS inverters, and our 5-stage RO achieved a low propagation delay of 30 ns/stage, which is also the lowest value among AOS and TFET related CMOS devices.</description><subject>Circuits</subject><subject>CMOS</subject><subject>Fabrication</subject><subject>Field effect transistors</subject><subject>Heterogeneous 3D integration</subject><subject>Indium tin oxide</subject><subject>Inverters</subject><subject>Logic gates</subject><subject>Metals</subject><subject>ring oscillator</subject><subject>Silicon</subject><subject>TFETs</subject><subject>Three-dimensional displays</subject><subject>tunnel FET</subject><issn>0741-3106</issn><issn>1558-0563</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2025</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpNkD1PwzAQhi0EEqWwMzD4D7ic4694RG2BSkFFavbIiS8iqHUqu1Dx73FFB6bT3fs-NzyE3HOYcQ72sVouZgUUaiZUUYJUF2TClSoZKC0uyQSM5Exw0NfkJqVPAC6lkRPSLnA3hnSI7jCMgY49rcYjex-PGGn9ERHZYthhSDl0Wzp_W2_oKnxjPGBMtHUJPc3YZqB7Vn-FgFv6vKypC56u6jUNLG-35Kp324R35zkldb7OX1m1flnNnyrW6cIyXloUiMo4b1uPaLTpeAceXI-Sd6Wx2nCphYNWOeic8G2neom-LXOr1GJK4O9tF8eUIvbNPg47F38aDs1JUZMVNSdFzVlRRh7-kAER_9VLoW1hxS-vFGIH</recordid><startdate>20250109</startdate><enddate>20250109</enddate><creator>Tong, Anyu</creator><creator>Wang, Kaifeng</creator><creator>Hu, Qianlan</creator><creator>Wang, Zhiyu</creator><creator>Xiong, Xiong</creator><creator>Yan, Shiwei</creator><creator>Zhu, Shenwu</creator><creator>Li, Qijun</creator><creator>Wu, Yongqin</creator><creator>Ren, Ye</creator><creator>Bu, Weihai</creator><creator>Huang, Qianqian</creator><creator>Wu, Yanqing</creator><creator>Huang, Ru</creator><general>IEEE</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><orcidid>https://orcid.org/0000-0002-3714-8581</orcidid><orcidid>https://orcid.org/0000-0002-5498-4135</orcidid><orcidid>https://orcid.org/0009-0007-3331-7716</orcidid><orcidid>https://orcid.org/0009-0001-8214-3341</orcidid><orcidid>https://orcid.org/0000-0003-2098-8864</orcidid><orcidid>https://orcid.org/0000-0003-2578-5214</orcidid></search><sort><creationdate>20250109</creationdate><title>Demonstration of Low-Power Three-Dimensional CMOS Inverters based on Si p-Tunnel FET and ITO n-FET</title><author>Tong, Anyu ; Wang, Kaifeng ; Hu, Qianlan ; Wang, Zhiyu ; Xiong, Xiong ; Yan, Shiwei ; Zhu, Shenwu ; Li, Qijun ; Wu, Yongqin ; Ren, Ye ; Bu, Weihai ; Huang, Qianqian ; Wu, Yanqing ; Huang, Ru</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c629-189e3ee57ad9bdee767c1c0d0afe41c879671463a0b5a0ca3dbc5f4edb8c0d863</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2025</creationdate><topic>Circuits</topic><topic>CMOS</topic><topic>Fabrication</topic><topic>Field effect transistors</topic><topic>Heterogeneous 3D integration</topic><topic>Indium tin oxide</topic><topic>Inverters</topic><topic>Logic gates</topic><topic>Metals</topic><topic>ring oscillator</topic><topic>Silicon</topic><topic>TFETs</topic><topic>Three-dimensional displays</topic><topic>tunnel FET</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Tong, Anyu</creatorcontrib><creatorcontrib>Wang, Kaifeng</creatorcontrib><creatorcontrib>Hu, Qianlan</creatorcontrib><creatorcontrib>Wang, Zhiyu</creatorcontrib><creatorcontrib>Xiong, Xiong</creatorcontrib><creatorcontrib>Yan, Shiwei</creatorcontrib><creatorcontrib>Zhu, Shenwu</creatorcontrib><creatorcontrib>Li, Qijun</creatorcontrib><creatorcontrib>Wu, Yongqin</creatorcontrib><creatorcontrib>Ren, Ye</creatorcontrib><creatorcontrib>Bu, Weihai</creatorcontrib><creatorcontrib>Huang, Qianqian</creatorcontrib><creatorcontrib>Wu, Yanqing</creatorcontrib><creatorcontrib>Huang, Ru</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><jtitle>IEEE electron device letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tong, Anyu</au><au>Wang, Kaifeng</au><au>Hu, Qianlan</au><au>Wang, Zhiyu</au><au>Xiong, Xiong</au><au>Yan, Shiwei</au><au>Zhu, Shenwu</au><au>Li, Qijun</au><au>Wu, Yongqin</au><au>Ren, Ye</au><au>Bu, Weihai</au><au>Huang, Qianqian</au><au>Wu, Yanqing</au><au>Huang, Ru</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Demonstration of Low-Power Three-Dimensional CMOS Inverters based on Si p-Tunnel FET and ITO n-FET</atitle><jtitle>IEEE electron device letters</jtitle><stitle>LED</stitle><date>2025-01-09</date><risdate>2025</risdate><spage>1</spage><epage>1</epage><pages>1-1</pages><issn>0741-3106</issn><eissn>1558-0563</eissn><coden>EDLEDZ</coden><abstract>In this work, low-power CMOS inverter and 5-stage ring oscillator (RO) are demonstrated based on heterogeneous 3D integration of vertically stacked FEOL p-type silicon tunnel FET (TFET) and BEOL n-type indium-tin-oxide (ITO) FET. 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| subjects | Circuits CMOS Fabrication Field effect transistors Heterogeneous 3D integration Indium tin oxide Inverters Logic gates Metals ring oscillator Silicon TFETs Three-dimensional displays tunnel FET |
| title | Demonstration of Low-Power Three-Dimensional CMOS Inverters based on Si p-Tunnel FET and ITO n-FET |
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