High-Performance Gate-All-Around FETs with 100 Ω Parasitic Resistance and 965 μA/μm On-State Current using Quasi-Self-Aligned Landing Pads

To overcome the challenges posed by the high parasitic resistance and poor driving performance induced by serious epitaxy defects in gate-all-around field-effect transistors (GAA FETs), a quasi-self-aligned landing pads ( QSA LPs ) technique is proposed, and defect-free connections among the multilayer stacked channels and single-crystal SiGe/Si superlattice source/drain (SD) structures are demonstrated in GAA FETs. When compared with devices with widely spaced LPs, reductions of 98.8% and 96.3% in the parasitic SD resistance ( R SD ) are observed for N/PFETs when using the QSA LPs technique, respectively. Therefore, the corresponding on-state current ( I on ) values are raised to 965 μA/μm and 669 μA/μm for 180 nm gate length N/PFETs, respectively. In addition, no significant changes are observed in the device subthreshold characteristics, including both the subthreshold swing and the on/off current ratios. The proposed scheme offers a new and promising approach to reduce the R SD values and enhance the performance of these advanced GAA devices.