n+Si/pGe Heterojunctions Fabricated by Low Temperature Ribbon Bonding With Passivating Interlayer
A bonding technique via passivating interlayer formation is proposed for bulk material heterojunction fabrication. n + Si/pGe heterojunctions were fabricated by a ribbon bonding with interfaces passivated by an amorphous interlayer. With a highest process temperature as low as 150 °C, the bonded jun...
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| Veröffentlicht in: | IEEE electron device letters 2017-06, Vol.38 (6), p.716-719 |
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| container_title | IEEE electron device letters |
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| creator | Liu, Tony Chi Kabuyanagi, Shoichi Nishimura, Tomonori Yajima, Takeaki Toriumi, Akira |
| description | A bonding technique via passivating interlayer formation is proposed for bulk material heterojunction fabrication. n + Si/pGe heterojunctions were fabricated by a ribbon bonding with interfaces passivated by an amorphous interlayer. With a highest process temperature as low as 150 °C, the bonded junctions exhibited rectifying characteristics with a turn-on voltage of 0.3 V as an ideal Si/Ge heterojunction and an ideality factor of 2.15. This technique shows a great potential for bulk material heterojunction formation, especially when ultimately abrupt junctions and low temperature processes are needed. |
| doi_str_mv | 10.1109/LED.2017.2699658 |
| format | Article |
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With a highest process temperature as low as 150 °C, the bonded junctions exhibited rectifying characteristics with a turn-on voltage of 0.3 V as an ideal Si/Ge heterojunction and an ideality factor of 2.15. This technique shows a great potential for bulk material heterojunction formation, especially when ultimately abrupt junctions and low temperature processes are needed.</description><identifier>ISSN: 0741-3106</identifier><identifier>EISSN: 1558-0563</identifier><identifier>DOI: 10.1109/LED.2017.2699658</identifier><identifier>CODEN: EDLEDZ</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Annealing ; Bonding ; Germanium ; Hafnium ; Heterojunctions ; interlayer ; Interlayers ; Low temperature ; passivation ; Silicon ; Temperature</subject><ispartof>IEEE electron device letters, 2017-06, Vol.38 (6), p.716-719</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2017</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c291t-56d1510031eb49532e9a1ed18ee1eca017d7f288cba621542499fc8b4edc880b3</citedby><cites>FETCH-LOGICAL-c291t-56d1510031eb49532e9a1ed18ee1eca017d7f288cba621542499fc8b4edc880b3</cites><orcidid>0000-0001-6868-8188</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/7914753$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/7914753$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Liu, Tony Chi</creatorcontrib><creatorcontrib>Kabuyanagi, Shoichi</creatorcontrib><creatorcontrib>Nishimura, Tomonori</creatorcontrib><creatorcontrib>Yajima, Takeaki</creatorcontrib><creatorcontrib>Toriumi, Akira</creatorcontrib><title>n+Si/pGe Heterojunctions Fabricated by Low Temperature Ribbon Bonding With Passivating Interlayer</title><title>IEEE electron device letters</title><addtitle>LED</addtitle><description>A bonding technique via passivating interlayer formation is proposed for bulk material heterojunction fabrication. n + Si/pGe heterojunctions were fabricated by a ribbon bonding with interfaces passivated by an amorphous interlayer. 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This technique shows a great potential for bulk material heterojunction formation, especially when ultimately abrupt junctions and low temperature processes are needed.</description><subject>Annealing</subject><subject>Bonding</subject><subject>Germanium</subject><subject>Hafnium</subject><subject>Heterojunctions</subject><subject>interlayer</subject><subject>Interlayers</subject><subject>Low temperature</subject><subject>passivation</subject><subject>Silicon</subject><subject>Temperature</subject><issn>0741-3106</issn><issn>1558-0563</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2017</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kF1LwzAUhoMoOKf3gjcBL6VbTpq0zaUf-4KCohMvQ5qeasbWzqRV9u_t2PDqwOF538N5CLkGNgJgapxPnkacQTriiVKJzE7IAKTMIiaT-JQMWCogioEl5-QihBVjIEQqBsTUd29uvJ0hnWOLvll1tW1dUwc6NYV31rRY0mJH8-aXLnGzRW_aziN9dUXR1PShqUtXf9IP137RFxOC-zHtfrGo-7a12aG_JGeVWQe8Os4heZ9Olo_zKH-eLR7v88hyBW0kkxIkMBYDFkLJmKMygCVkiIDW9J-VacWzzBYm4SAFF0pVNisEljbLWBEPye2hd-ub7w5Dq1dN5-v-pAbFOE9lLFhPsQNlfROCx0pvvdsYv9PA9F6k7kXqvUh9FNlHbg4Rh4j_eKpA9JXxH3YGbvk</recordid><startdate>20170601</startdate><enddate>20170601</enddate><creator>Liu, Tony Chi</creator><creator>Kabuyanagi, Shoichi</creator><creator>Nishimura, Tomonori</creator><creator>Yajima, Takeaki</creator><creator>Toriumi, Akira</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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| source | IEEE Electronic Library (IEL) |
| subjects | Annealing Bonding Germanium Hafnium Heterojunctions interlayer Interlayers Low temperature passivation Silicon Temperature |
| title | n+Si/pGe Heterojunctions Fabricated by Low Temperature Ribbon Bonding With Passivating Interlayer |
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