High-Performance Silicon Nanowire Gate-All-Around nMOSFETs Fabricated on Bulk Substrate Using CMOS-Compatible Process

In this letter, a novel self-aligned CMOS-compatible method for the fabrication of gate-all-around silicon nanowire MOSFETs (GAA SNWFETs) on bulk substrate has been proposed. The fabricated SNWFET featuring 33-nm gate length and 7-nm diameter shows the highest driving current ( I on = 2500 μA/μm at...

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Veröffentlicht in:	IEEE electron device letters 2010-12, Vol.31 (12), p.1377-1379
Hauptverfasser:	Song, Yi, Zhou, Huajie, Xu, Qiuxia, Niu, Jiebin, Yan, Jiang, Zhao, Chao, Zhong, Huicai
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Bulk gate-all-around silicon nanowire MOSFETs (GAA SNWFETs) CMOS integrated circuits Cross-disciplinary physics: materials science rheology Design. Technologies. Operation analysis. Testing Devices Electronics Exact sciences and technology Gates Integrated circuits Logic gates Materials science MOSFETs Nanocomposites Nanomaterials Nanoscale materials and structures: fabrication and characterization Nanostructure Nanostructured materials Nanowires Optimization Oxidation parasitic effects Physics Quantum wires Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon substrates stress-limited oxidation Substrates Transistors volume inversion
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Zusammenfassung:	In this letter, a novel self-aligned CMOS-compatible method for the fabrication of gate-all-around silicon nanowire MOSFETs (GAA SNWFETs) on bulk substrate has been proposed. The fabricated SNWFET featuring 33-nm gate length and 7-nm diameter shows the highest driving current ( I on = 2500 μA/μm at V ds = V gs = 1.0 V) among previously reported data and achieves high I on / I off ratio of 10 5 , lightening the promise for high performance and strong scalability of GAA SNWFETs. The process details and optimization procedure are extensively discussed.
ISSN:	0741-3106 1558-0563
DOI:	10.1109/LED.2010.2080256