Investigation on the Retention Reliability of Scaled \hbox/\hbox\hbox/\hbox Inter-Poly Dielectrics for nand Flash Cell Arrays

We investigate the retention reliability of a 51-nm-node 16-GB nand Flash cell transistor comprising SiO 2 /Al x O y /SiO 2 inter-poly dielectric (OAO IPD). Despite the fact that OAO IPD retains low trapping rate being beneficial to retention reliability, the trap sites are located on shallow energy level, yielding a large amount of trap-assisted tunneling current at high temperature. Therefore, experimental results show two incompatible data retention characteristics of OAO IPD, namely, 33% worse V TH shift at 200°C 2-h bake and 53% improved V TH shift after one week at 25°C, when compared to the case of ONO IPD.