Low-Threshold-Voltage TaN/Ir/LaTiO p-MOSFETs Incorporating Low-Temperature-Formed Shallow Junctions

We demonstrate a low threshold voltage (Vt) of -0.17 V and good hole mobility (54 cm 2 /V middot s at 0.8 MV/cm) in TaN/Ir/LaTiO p-MOSFETs at an equivalent oxide thickness of only 0.66 nm. This was achieved by using Ni-induced solid-phase diffusion of SiO 2 -covered Ni/Ga which reduced the high-kapp...

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Veröffentlicht in:	IEEE electron device letters 2009-06, Vol.30 (6), p.681-683
Hauptverfasser:	Lin, S.H., Chen, W.B., Cheng, C.H., Yeh, F.S., Chin, A.
Format:	Artikel
Sprache:	eng
Schlagworte:	Annealing Applied sciences Channel bank filters Compound structure devices Design. Technologies. Operation analysis. Testing Dielectric devices Dielectrics Electronics Equivalence Exact sciences and technology Gallium Integrated circuits Interface reactions Iridium LaTiO low V_{t} Mechanical engineering MOSFET circuits Nickel Oxides Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon dioxide Solid lasers solid-phase diffusion (SPD) Temperature dependence Thermal stability Threshold voltage Transistors Very large scale integration
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Zusammenfassung:	We demonstrate a low threshold voltage (Vt) of -0.17 V and good hole mobility (54 cm 2 /V middot s at 0.8 MV/cm) in TaN/Ir/LaTiO p-MOSFETs at an equivalent oxide thickness of only 0.66 nm. This was achieved by using Ni-induced solid-phase diffusion of SiO 2 -covered Ni/Ga which reduced the high-kappa dielectric interfacial reactions. This approach, along with its self-aligned and gate-first process, is compatible with current VLSI technology.
ISSN:	0741-3106 1558-0563
DOI:	10.1109/LED.2009.2020307