Mechanism of positive-bias temperature instability in sub-1-nm TaN/HfN/HfO/sub 2/ gate stack with low preexisting traps

In this letter, the positive-bias temperature instability (PBTI) characteristics of a TaN/HfN/HfO/sub 2/ gate stack with an equivalent oxide thickness (EOT) of 0.95 nm and low preexisting traps are studied. The negligible PBTI at room temperature, the so-called "turn-around" phenomenon, and the negative shifts of the threshold voltage (V/sub t/) are observed. A modified reaction-diffusion (R-D) model, which is based on the electric stress induced defect generation (ESIDG) mechanism, is proposed to explain the above-mentioned PBTI characteristics. In this modified R-D model, PBTI is attributed to the electron-induced breaking of Si-O bonds at interfacial layer (IL) between HfO/sub 2/ and Si substrate and the diffusion/drift of oxygen ions (O/sup -/) from Si-O bonds into HfO/sub 2/ layer under positive-bias temperature stressing. The ESIDG mechanism is responsible for the breaking of Si-O bonds. The measured activation energy (E/sub a/) is consistent with the one predicted by the ESIDG mechanism.