A Wireline Transceiver With 3-bit per Symbol Using Common-Mode NRZ and Differential-Mode PAM-4 Signaling Techniques

This article presents a wireline transceiver using 3-bit per symbol signaling techniques that can simultaneously modulate and demodulate the common-mode (CM) 1-bit non-return to zero (NRZ) and differential-mode (DM) 2-bit pulse amplitude modulation 4 (PAM-4) signals (CMDM-8). The driver of the trans...

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Veröffentlicht in:IEEE journal of solid-state circuits 2024-08, Vol.59 (8), p.2518-2528
Hauptverfasser: Sim, Jincheol, Choi, Jonghyuck, Kwon, Youngwook, Park, Seungwoo, Kim, Seongcheol, Sim, Changmin, Shin, Hwaseok, So, Junseob, Lee, Seonbeen, Kim, Chulwoo
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Sprache:eng
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Zusammenfassung:This article presents a wireline transceiver using 3-bit per symbol signaling techniques that can simultaneously modulate and demodulate the common-mode (CM) 1-bit non-return to zero (NRZ) and differential-mode (DM) 2-bit pulse amplitude modulation 4 (PAM-4) signals (CMDM-8). The driver of the transmitter (TX) configured with two different types of current mode PAM-4 drivers generates CMDM-8, a mixed signal of single NRZ and differential PAM-4. If the common-mode voltage (VCM) of the two types of PAM-4 drivers is different, the VCM of the CMDM-8 signals swings between the two different VCM even if the two PAM-4 drivers generate the identical PAM-4 signal in the DM. Therefore, the TX can generate the NRZ signal in the CM while transmitting the PAM-4 signals. At the receiver (RX), the CMDM-8, which combines NRZ and PAM-4 signals, is divided into NRZ and PAM-4 signals in the analog front end. The divided analog signals are converted to the 3-bit digital data in the decoder. The 3-bit decoder recovers the NRZ and PAM-4 signals to the original data. When 2 bits are recovered from the PAM-4 signal, the VCM of the PAM-4 signal is not constant due to the residual NRZ signal. Thus, the proposed PAM-4 decoder applies an offset-based PAM-4 decoding method to achieve robustness against the VCM change. The prototype was fabricated with a 28-nm CMOS technology and had a maximum data rate of 48 Gb/s. The transceiver with an area of 0.117 mm2 enabled a bit error rate (BER) of 10 ^{-12} at 9.08-dB attenuation and had a power efficiency of 4.40 pJ/bit.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2024.3358337