A Bit-Serial, Compute-in-SRAM Design Featuring Hybrid-Integrating ADCs and Input Dependent Binary Scaled Precharge Eliminating DACs for Energy-Efficient DNN Inference

The major challenge faced by modern compute-in-memory (CIM) designs is that they rely heavily on mixed-signal data converters such as digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) that contribute to \sim 15% area and \sim 50% energy of the overall macro and are susceptible to non-linearities, leakage, and process variations, which causes deep neural network (DNN) inference/training accuracy loss. As DNN models increase in size, the number of DACs steps required per inference increases exponentially. This work proposes a four-pronged approach to address the challenges in CIM designs: 1) binary-weighted-bitline-precharge scheme utilizing dedicated reference voltages to perform input bit-serial multiplication in the charge domain, eliminating the need for dedicated DAC circuits; 2) leakage-tolerant, input-dependent-bitline-keeper circuits that maintain the local-bitline voltages; 3) hybrid-charge-sharing-based integrating-ADCs to improve the ADC conversion time by leveraging the reference voltages, thereby improving ADC latency while achieving a compact ADC design; and 4) efficient data movement and utilization of analog-to-digital co-computation. Fabricated in TSMC 65 nm, the experimental results for the compute-in-static-RAM (CISRAM) silicon prototype show an average macro energy efficiency of 153-2453.76 TOPs/W. The average macro energy efficiency is 2.3 \times more than the latest state of the art mentioned in the comparison table.