A 1-Tb 4-b/cell 4-Plane 162-Layer 3-D Flash Memory With 2.4-Gb/s IO Interface
A 1 Tb 4-b/cell 162-layer 3-D flash memory achieves 15-Gb/mm2 areal density and delivers program throughput up to 60 MB/s and the best case tR of 65 \mu \text{s} by employing 8-kB wordline (WL) central stair structure and contact-through-WL (CTW) architecture. IO speed of 2.4 Gb/s with low tapped...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2023-01, Vol.58 (1), p.316-328 |
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| creator | Yuh, Jong Hak Li, Yen-Lung Jason Li, Heguang Oyama, Yoshihiro Hsu, Cynthia Anantula, Pradeep Jeong, Gwang Yeong Stanley Amarnath, Anirudh Darne, Siddhesh Bhatia, Sneha Tang, Tianyu Arya, Aditya Rastogi, Naman Ookuma, Naoki Mizukoshi, Hiroyuki Yap, Alex Wang, Demin Kim, Steve Wu, Yonggang Peng, Min Lu, Jason Ip, Tommy Malhotra, Seema Han, Taekeun Okumura, Masatoshi Liu, Jiwen Sohn, Jeongduk John Chibvongodze, Hardwell Balaga, Muralikrishna Matsuda, Akihiro Chen, Chen K. V., Indra G., V. S. N. K. Chaitanya Ramachandra, Venky Kato, Yosuke Kumar, Ravi J. Wang, Huijuan Moogat, Farookh Yoon, In-Soo Kanda, Kazushige Shimizu, Takahiro Shibata, Noboru Yanagidaira, Kosuke Kodama, Takuyo Fukuda, Ryo Hirashima, Yasuhiro Abe, Mitsuhiro |
| description | A 1 Tb 4-b/cell 162-layer 3-D flash memory achieves 15-Gb/mm2 areal density and delivers program throughput up to 60 MB/s and the best case tR of 65 \mu \text{s} by employing 8-kB wordline (WL) central stair structure and contact-through-WL (CTW) architecture. IO speed of 2.4 Gb/s with low tapped termination/center tapped termination (LTT/CTT) combo driver is supported. This article also discusses data transfer energy reduction using VCCQ domain design and data bus inversion (DBI) technique. Novel time division peak power management (TD-PPM) feature can reduce system peak current while maximizing system performance. Cache and IO discrete Fourier transform (DFT) enable a high-speed testing at wafer level for test cost reduction. |
| doi_str_mv | 10.1109/JSSC.2022.3193326 |
| format | Article |
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V., Indra ; G., V. S. N. K. Chaitanya ; Ramachandra, Venky ; Kato, Yosuke ; Kumar, Ravi J. ; Wang, Huijuan ; Moogat, Farookh ; Yoon, In-Soo ; Kanda, Kazushige ; Shimizu, Takahiro ; Shibata, Noboru ; Yanagidaira, Kosuke ; Kodama, Takuyo ; Fukuda, Ryo ; Hirashima, Yasuhiro ; Abe, Mitsuhiro</creator><creatorcontrib>Yuh, Jong Hak ; Li, Yen-Lung Jason ; Li, Heguang ; Oyama, Yoshihiro ; Hsu, Cynthia ; Anantula, Pradeep ; Jeong, Gwang Yeong Stanley ; Amarnath, Anirudh ; Darne, Siddhesh ; Bhatia, Sneha ; Tang, Tianyu ; Arya, Aditya ; Rastogi, Naman ; Ookuma, Naoki ; Mizukoshi, Hiroyuki ; Yap, Alex ; Wang, Demin ; Kim, Steve ; Wu, Yonggang ; Peng, Min ; Lu, Jason ; Ip, Tommy ; Malhotra, Seema ; Han, Taekeun ; Okumura, Masatoshi ; Liu, Jiwen ; Sohn, Jeongduk John ; Chibvongodze, Hardwell ; Balaga, Muralikrishna ; Matsuda, Akihiro ; Chen, Chen ; K. V., Indra ; G., V. S. N. K. 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IO speed of 2.4 Gb/s with low tapped termination/center tapped termination (LTT/CTT) combo driver is supported. This article also discusses data transfer energy reduction using VCCQ domain design and data bus inversion (DBI) technique. Novel time division peak power management (TD-PPM) feature can reduce system peak current while maximizing system performance. Cache and IO discrete Fourier transform (DFT) enable a high-speed testing at wafer level for test cost reduction.</description><subject>3-D flash</subject><subject>Ash</subject><subject>BiCS flash</subject><subject>Computer architecture</subject><subject>Data transfer (computers)</subject><subject>Decoding</subject><subject>discrete Fourier transform (DFT)</subject><subject>Flash memory (computers)</subject><subject>Fourier transforms</subject><subject>IO design</subject><subject>Metals</subject><subject>NAND</subject><subject>peak power management (PPM)</subject><subject>Pins</subject><subject>Power management</subject><subject>program throughput</subject><subject>Throughput</subject><subject>Transistors</subject><subject>User interfaces</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2023</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kMFOAjEQhhujiYg-gPHSxHOXznS72x4JCmIgmIDRW9PutgGysNpdDry9SyCe5p_k-2eSj5BH4AkA14P35XKUIEdMBGghMLsiPZBSMcjF9zXpcQ6KaeT8ltw1zbZb01RBj8yHFNjK0ZS5QeGrqgsfld17ChmymT36SAV7oePKNms697s6HunXpl1TTFI2cYOGThd0um99DLbw9-Qm2KrxD5fZJ5_j19Xojc0Wk-loOGMFatGyUuksdcpluZfWZrlOkRdKyFxKtIqXRXBQQlDOlQGDhbIMeZlaVahMaAQl-uT5fPcn1r8H37RmWx_ivntpMJcqR4EoOwrOVBHrpok-mJ-42dl4NMDNyZo5WTMna-Zires8nTsb7_0_r5WUQoP4AytQY1Q</recordid><startdate>20230101</startdate><enddate>20230101</enddate><creator>Yuh, Jong Hak</creator><creator>Li, Yen-Lung Jason</creator><creator>Li, Heguang</creator><creator>Oyama, Yoshihiro</creator><creator>Hsu, Cynthia</creator><creator>Anantula, Pradeep</creator><creator>Jeong, Gwang Yeong Stanley</creator><creator>Amarnath, Anirudh</creator><creator>Darne, Siddhesh</creator><creator>Bhatia, Sneha</creator><creator>Tang, Tianyu</creator><creator>Arya, Aditya</creator><creator>Rastogi, Naman</creator><creator>Ookuma, Naoki</creator><creator>Mizukoshi, Hiroyuki</creator><creator>Yap, Alex</creator><creator>Wang, Demin</creator><creator>Kim, Steve</creator><creator>Wu, Yonggang</creator><creator>Peng, Min</creator><creator>Lu, Jason</creator><creator>Ip, Tommy</creator><creator>Malhotra, Seema</creator><creator>Han, Taekeun</creator><creator>Okumura, Masatoshi</creator><creator>Liu, Jiwen</creator><creator>Sohn, Jeongduk John</creator><creator>Chibvongodze, Hardwell</creator><creator>Balaga, Muralikrishna</creator><creator>Matsuda, Akihiro</creator><creator>Chen, Chen</creator><creator>K. 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IO speed of 2.4 Gb/s with low tapped termination/center tapped termination (LTT/CTT) combo driver is supported. This article also discusses data transfer energy reduction using VCCQ domain design and data bus inversion (DBI) technique. Novel time division peak power management (TD-PPM) feature can reduce system peak current while maximizing system performance. Cache and IO discrete Fourier transform (DFT) enable a high-speed testing at wafer level for test cost reduction.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/JSSC.2022.3193326</doi><tpages>13</tpages><orcidid>https://orcid.org/0000-0002-8223-9108</orcidid><orcidid>https://orcid.org/0000-0003-0254-6528</orcidid><orcidid>https://orcid.org/0000-0001-7699-6367</orcidid></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 2023-01, Vol.58 (1), p.316-328 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_crossref_primary_10_1109_JSSC_2022_3193326 |
| source | IEEE Electronic Library (IEL) |
| subjects | 3-D flash Ash BiCS flash Computer architecture Data transfer (computers) Decoding discrete Fourier transform (DFT) Flash memory (computers) Fourier transforms IO design Metals NAND peak power management (PPM) Pins Power management program throughput Throughput Transistors User interfaces |
| title | A 1-Tb 4-b/cell 4-Plane 162-Layer 3-D Flash Memory With 2.4-Gb/s IO Interface |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-13T21%3A08%3A00IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%201-Tb%204-b/cell%204-Plane%20162-Layer%203-D%20Flash%20Memory%20With%202.4-Gb/s%20IO%20Interface&rft.jtitle=IEEE%20journal%20of%20solid-state%20circuits&rft.au=Yuh,%20Jong%20Hak&rft.date=2023-01-01&rft.volume=58&rft.issue=1&rft.spage=316&rft.epage=328&rft.pages=316-328&rft.issn=0018-9200&rft.eissn=1558-173X&rft.coden=IJSCBC&rft_id=info:doi/10.1109/JSSC.2022.3193326&rft_dat=%3Cproquest_RIE%3E2758723225%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2758723225&rft_id=info:pmid/&rft_ieee_id=9855391&rfr_iscdi=true |