A 1-Tb 4-b/cell 4-Plane 162-Layer 3-D Flash Memory With 2.4-Gb/s IO Interface

A 1 Tb 4-b/cell 162-layer 3-D flash memory achieves 15-Gb/mm2 areal density and delivers program throughput up to 60 MB/s and the best case tR of 65 \mu \text{s} by employing 8-kB wordline (WL) central stair structure and contact-through-WL (CTW) architecture. IO speed of 2.4 Gb/s with low tapped...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2023-01, Vol.58 (1), p.316-328
Hauptverfasser:	Yuh, Jong Hak, Li, Yen-Lung Jason, Li, Heguang, Oyama, Yoshihiro, Hsu, Cynthia, Anantula, Pradeep, Jeong, Gwang Yeong Stanley, Amarnath, Anirudh, Darne, Siddhesh, Bhatia, Sneha, Tang, Tianyu, Arya, Aditya, Rastogi, Naman, Ookuma, Naoki, Mizukoshi, Hiroyuki, Yap, Alex, Wang, Demin, Kim, Steve, Wu, Yonggang, Peng, Min, Lu, Jason, Ip, Tommy, Malhotra, Seema, Han, Taekeun, Okumura, Masatoshi, Liu, Jiwen, Sohn, Jeongduk John, Chibvongodze, Hardwell, Balaga, Muralikrishna, Matsuda, Akihiro, Chen, Chen, K. V., Indra, G., V. S. N. K. Chaitanya, Ramachandra, Venky, Kato, Yosuke, Kumar, Ravi J., Wang, Huijuan, Moogat, Farookh, Yoon, In-Soo, Kanda, Kazushige, Shimizu, Takahiro, Shibata, Noboru, Yanagidaira, Kosuke, Kodama, Takuyo, Fukuda, Ryo, Hirashima, Yasuhiro, Abe, Mitsuhiro
Format:	Artikel
Sprache:	eng
Schlagworte:	3-D flash Ash BiCS flash Computer architecture Data transfer (computers) Decoding discrete Fourier transform (DFT) Flash memory (computers) Fourier transforms IO design Metals NAND peak power management (PPM) Pins Power management program throughput Throughput Transistors User interfaces
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Zusammenfassung:	A 1 Tb 4-b/cell 162-layer 3-D flash memory achieves 15-Gb/mm2 areal density and delivers program throughput up to 60 MB/s and the best case tR of 65 \mu \text{s} by employing 8-kB wordline (WL) central stair structure and contact-through-WL (CTW) architecture. IO speed of 2.4 Gb/s with low tapped termination/center tapped termination (LTT/CTT) combo driver is supported. This article also discusses data transfer energy reduction using VCCQ domain design and data bus inversion (DBI) technique. Novel time division peak power management (TD-PPM) feature can reduce system peak current while maximizing system performance. Cache and IO discrete Fourier transform (DFT) enable a high-speed testing at wafer level for test cost reduction.
ISSN:	0018-9200 1558-173X
DOI:	10.1109/JSSC.2022.3193326