A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET
This article presents analysis, design details, and measurement result of a 224-Gb/s four-level pulse amplitude modulation (PAM-4) transmitter (TX) consisting of a 7-bit voltage digital-to-analog converter (DAC) driver, digital 8-tap feed-forward equalizer (FFE), and a 28-GHz inductively peaked cloc...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2022-01, Vol.57 (1), p.6-20 |
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| creator | Kim, Jihwan Kundu, Sandipan Balankutty, Ajay Beach, Matthew Kim, Bong Chan Kim, Stephen T. Liu, Yutao Murthy, Savyasaachi Keshava Wali, Priya Yu, Kai Kim, Hyung Seok Liu, Chuan-Chang Shin, Dongseok Cohen, Ariel Segal, Yoav Fan, Yongping Li, Peng O'Mahony, Frank |
| description | This article presents analysis, design details, and measurement result of a 224-Gb/s four-level pulse amplitude modulation (PAM-4) transmitter (TX) consisting of a 7-bit voltage digital-to-analog converter (DAC) driver, digital 8-tap feed-forward equalizer (FFE), and a 28-GHz inductively peaked clock distribution network. The TX DAC uses quarter-rate clocking with a 4:1 pulse-based data serialization architecture. Design techniques for generating and distributing low-jitter CMOS clocks up to 29 GHz, timing closure in the serializer, 112-Gbaud 4:1 data MUX using 1-UI pulse generator, and bandwidth/return loss/group delay optimized output pad network using a 9th-order LC filter are described. Fabricated in the Intel 10-nm FinFET process technology, the TX demonstrates random jitter (RJ) of 65 fs rms with nominal output swing of 1.0~V_{\mathrm {ppd}} at 224 Gb/s achieving 1.88-pJ/b energy efficiency including an on-die LC phase-locked loop (PLL). To the best of authors' knowledge, this TX achieved the highest data rate with the lowest RJ for CMOS SerDes TXs reported to date. |
| doi_str_mv | 10.1109/JSSC.2021.3108969 |
| format | Article |
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The TX DAC uses quarter-rate clocking with a 4:1 pulse-based data serialization architecture. Design techniques for generating and distributing low-jitter CMOS clocks up to 29 GHz, timing closure in the serializer, 112-Gbaud 4:1 data MUX using 1-UI pulse generator, and bandwidth/return loss/group delay optimized output pad network using a 9th-order LC filter are described. Fabricated in the Intel 10-nm FinFET process technology, the TX demonstrates random jitter (RJ) of 65 fs rms with nominal output swing of <inline-formula> <tex-math notation="LaTeX">1.0~V_{\mathrm {ppd}} </tex-math></inline-formula> at 224 Gb/s achieving 1.88-pJ/b energy efficiency including an on-die LC phase-locked loop (PLL). To the best of authors' knowledge, this TX achieved the highest data rate with the lowest RJ for CMOS SerDes TXs reported to date.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2021.3108969</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>10 nm ; 4:1 serializer ; <italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">LC filter ; Bandwidth ; Clocks ; CMOS ; Digital to analog converters ; digital-to-analog converter (DAC) ; Equalizers ; feed-forward equalizer (FFE) ; FinFET ; four-level pulse amplitude modulation (PAM-4) ; Group delay ; I/O ; Jitter ; Linearity ; matching network ; Phase locked loops ; Pulse amplitude modulation ; Pulse generators ; quarter rate ; SerDes ; Timing ; transmitter (TX) ; Transmitters ; Vibration</subject><ispartof>IEEE journal of solid-state circuits, 2022-01, Vol.57 (1), p.6-20</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2022</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c293t-264545d3de30254039d8f2e3de64e1314f4e95ea647016d9d8534b5f8e7891b73</citedby><cites>FETCH-LOGICAL-c293t-264545d3de30254039d8f2e3de64e1314f4e95ea647016d9d8534b5f8e7891b73</cites><orcidid>0000-0003-0014-2626 ; 0000-0002-5599-2997 ; 0000-0001-7961-9452 ; 0000-0003-2386-7945 ; 0000-0002-1996-9319 ; 0000-0001-5914-2765 ; 0000-0003-3806-6913</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9537159$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9537159$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Kim, Jihwan</creatorcontrib><creatorcontrib>Kundu, Sandipan</creatorcontrib><creatorcontrib>Balankutty, Ajay</creatorcontrib><creatorcontrib>Beach, Matthew</creatorcontrib><creatorcontrib>Kim, Bong Chan</creatorcontrib><creatorcontrib>Kim, Stephen T.</creatorcontrib><creatorcontrib>Liu, Yutao</creatorcontrib><creatorcontrib>Murthy, Savyasaachi Keshava</creatorcontrib><creatorcontrib>Wali, Priya</creatorcontrib><creatorcontrib>Yu, Kai</creatorcontrib><creatorcontrib>Kim, Hyung Seok</creatorcontrib><creatorcontrib>Liu, Chuan-Chang</creatorcontrib><creatorcontrib>Shin, Dongseok</creatorcontrib><creatorcontrib>Cohen, Ariel</creatorcontrib><creatorcontrib>Segal, Yoav</creatorcontrib><creatorcontrib>Fan, Yongping</creatorcontrib><creatorcontrib>Li, Peng</creatorcontrib><creatorcontrib>O'Mahony, Frank</creatorcontrib><title>A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>This article presents analysis, design details, and measurement result of a 224-Gb/s four-level pulse amplitude modulation (PAM-4) transmitter (TX) consisting of a 7-bit voltage digital-to-analog converter (DAC) driver, digital 8-tap feed-forward equalizer (FFE), and a 28-GHz inductively peaked clock distribution network. The TX DAC uses quarter-rate clocking with a 4:1 pulse-based data serialization architecture. Design techniques for generating and distributing low-jitter CMOS clocks up to 29 GHz, timing closure in the serializer, 112-Gbaud 4:1 data MUX using 1-UI pulse generator, and bandwidth/return loss/group delay optimized output pad network using a 9th-order LC filter are described. Fabricated in the Intel 10-nm FinFET process technology, the TX demonstrates random jitter (RJ) of 65 fs rms with nominal output swing of <inline-formula> <tex-math notation="LaTeX">1.0~V_{\mathrm {ppd}} </tex-math></inline-formula> at 224 Gb/s achieving 1.88-pJ/b energy efficiency including an on-die LC phase-locked loop (PLL). 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The TX DAC uses quarter-rate clocking with a 4:1 pulse-based data serialization architecture. Design techniques for generating and distributing low-jitter CMOS clocks up to 29 GHz, timing closure in the serializer, 112-Gbaud 4:1 data MUX using 1-UI pulse generator, and bandwidth/return loss/group delay optimized output pad network using a 9th-order LC filter are described. Fabricated in the Intel 10-nm FinFET process technology, the TX demonstrates random jitter (RJ) of 65 fs rms with nominal output swing of <inline-formula> <tex-math notation="LaTeX">1.0~V_{\mathrm {ppd}} </tex-math></inline-formula> at 224 Gb/s achieving 1.88-pJ/b energy efficiency including an on-die LC phase-locked loop (PLL). To the best of authors' knowledge, this TX achieved the highest data rate with the lowest RJ for CMOS SerDes TXs reported to date.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/JSSC.2021.3108969</doi><tpages>15</tpages><orcidid>https://orcid.org/0000-0003-0014-2626</orcidid><orcidid>https://orcid.org/0000-0002-5599-2997</orcidid><orcidid>https://orcid.org/0000-0001-7961-9452</orcidid><orcidid>https://orcid.org/0000-0003-2386-7945</orcidid><orcidid>https://orcid.org/0000-0002-1996-9319</orcidid><orcidid>https://orcid.org/0000-0001-5914-2765</orcidid><orcidid>https://orcid.org/0000-0003-3806-6913</orcidid></addata></record> |
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| subjects | 10 nm 4:1 serializer <italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">LC filter Bandwidth Clocks CMOS Digital to analog converters digital-to-analog converter (DAC) Equalizers feed-forward equalizer (FFE) FinFET four-level pulse amplitude modulation (PAM-4) Group delay I/O Jitter Linearity matching network Phase locked loops Pulse amplitude modulation Pulse generators quarter rate SerDes Timing transmitter (TX) Transmitters Vibration |
| title | A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET |
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