Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control

Single-inductor multiple-output (SIMO) voltage regulators allow multiple voltage domains to share a single inductor, thus representing a domain-scalable approach to energy-efficient integrated voltage regulation (IVR). However, poor transient response and significant supply voltage ( {V_{{\mathrm {dd}}} ) ripple in SIMO regulators induce severe voltage margins. This article quantifies the prohibitive energy-efficiency impact of these margins and proposes two techniques to address them: dynamic droop allocation (DDA) through concurrent domain- {V_{{\mathrm {dd}}} control and adaptive clocking using the UniCap architecture. We demonstrate the effectiveness of both techniques on an integrated four-domain SIMO system on chip (SoC) in 65-nm CMOS. Measurements indicate that, compared to conventional SIMO implementations, {V_{{\mathrm {dd}}} guardband reductions obtained by UniCaP (98%) and DDA (40%) reduce total system power draw by 53% and 31% respectively.