A 60 dB SNDR 35 MS/s SAR ADC With Comparator-Noise-Based Stochastic Residue Estimation

A 60 dB SNDR 35 MS/s SAR ADC With Comparator-Noise-Based Stochastic Residue Estimation

We present a SAR ADC with comparator-noise-based stochastic residue estimation. The circuit uses a 9 cycle SAR converter to generate a residue, which is then quantized by clocking 16 noisy comparators four times each and digitally calculating the most likely input voltage for the obtained distributi...

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Veröffentlicht in:IEEE journal of solid-state circuits 2015-09, Vol.50 (9), p.2002-2011
Hauptverfasser: Verbruggen, Bob, Tsouhlarakis, Jorgo, Yamamoto, Takaya, Iriguchi, Masao, Martens, Ewout, Craninckx, Jan
Format: Artikel
Sprache:eng
Schlagworte:
Accuracy
Analog-digital converter (ADC)
comparator noise
Energy consumption
Estimation
Noise
power efficiency
Quantization (signal)
Stochastic processes
stochastic quantization
successive approximation
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Beschreibung
Zusammenfassung:We present a SAR ADC with comparator-noise-based stochastic residue estimation. The circuit uses a 9 cycle SAR converter to generate a residue, which is then quantized by clocking 16 noisy comparators four times each and digitally calculating the most likely input voltage for the obtained distribution of zeros and ones. The ADC achieves a 60.9 dB SNDR for a near-Nyquist input at 35 MS/s for a purely dynamic power consumption of 12 μW/MHz.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2015.2422781