A WCDMA/WLAN Digital Polar Transmitter With Low-Noise ADPLL, Wideband PM/AM Modulator, and Linearized PA
This paper presents a single-chip digital-intensive polar transmitter for WCDMA and WLAN integrating a low-phase-noise all-digital phase-locked loop (ADPLL), a digitally-controlled wideband phase/amplitude modulator, and a calibration-free high-linearity power amplifier. From the ADPLL, the 1.7-2.5...
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Veröffentlicht in: | IEEE journal of solid-state circuits 2015-07, Vol.50 (7), p.1645-1656 |
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Format: | Artikel |
Sprache: | eng |
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Zusammenfassung: | This paper presents a single-chip digital-intensive polar transmitter for WCDMA and WLAN integrating a low-phase-noise all-digital phase-locked loop (ADPLL), a digitally-controlled wideband phase/amplitude modulator, and a calibration-free high-linearity power amplifier. From the ADPLL, the 1.7-2.5 GHz LO signal is generated together with a ÷1.5 frequency divider to eliminate DCO pulling. The phase noise of the ADPLL is optimized by using a linearized stochastic TDC with 3 ps resolution and a Class-C quadrature DCO (QDCO) with embedded quadrature phase shifter and quantization-noise filter. A 2-segment ΣΔ switching phase modulator enhances the PM bandwidth up to 200 MHz, and a digital polar amplifier employs AM-replica linearization to eliminate AM pre-distortion. The TX achieves a -1 dB output compression point of 22.8 dBm with an overall system efficiency of 27.6% and measures EVM of 4% for a 20 MHz 64-QAM signal at an output power of 13.8 dBm. |
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ISSN: | 0018-9200 1558-173X |
DOI: | 10.1109/JSSC.2015.2413846 |