The 10th Generation 16-Core SPARC64™ Processor for Mission Critical UNIX Server

A 10th generation SPARC64 processor, fabricated in enhanced 28 nm CMOS, runs at 3.0 GHz and contains 16 cores with 24 MB shared L2 cache and system/DDR3/PCIe interfaces in 588 mm 2 die area. Using H-tree clock distribution network with shield wires, the average clock skew is minimized to 20 ps. Two-...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Veröffentlicht in:	IEEE journal of solid-state circuits 2014-01, Vol.49 (1), p.32-40
Hauptverfasser:	Kan, Ryuji, Tanaka, Tomohiro, Sugizaki, Go, Ishizaka, Kinya, Nishiyama, Ryuichi, Sakabayashi, Sota, Koyanagi, Yoichi, Iwatsuki, Ryuji, Hayasaka, Kazumi, Uemura, Taiki, Ito, Gaku, Ozeki, Yoshitomo, Adachi, Hiroyuki, Furuya, Kazuhiro, Motokurumada, Tsuyoshi
Format:	Artikel
Sprache:	eng
Schlagworte:	Clock distribution Clocks computer architecture Ground penetrating radar high-speed SerDes Latches microprocessor Pipelines register file Registers reliability soft error SPARC test Timing Wires
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Beschreibung
Zusammenfassung:	A 10th generation SPARC64 processor, fabricated in enhanced 28 nm CMOS, runs at 3.0 GHz and contains 16 cores with 24 MB shared L2 cache and system/DDR3/PCIe interfaces in 588 mm 2 die area. Using H-tree clock distribution network with shield wires, the average clock skew is minimized to 20 ps. Two-step read structure of GPR enables out-of-order execution across register windows. A large SMP system of up to 64 CPUs with ccNUMA uses a newly developed 14.5 GB/s SerDes. Column separation, alternate placement of master and slave latches and well slits are used to mitigate soft errors especially for multi-bit upsets. SER reduction is observed by neutron irradiation experiments.
ISSN:	0018-9200 1558-173X
DOI:	10.1109/JSSC.2013.2284650