An Integral Path Self-Calibration Scheme for a Dual-Loop PLL

An integral-path self-calibration scheme is introduced as part of a 20.1 GHz to 26.7 GHz low-noise PLL in 32 nm CMOS SOI. A dual-loop architecture in combination with an integral path measurement and correction scheme desensitizes the loop transfer function to the VCO's small signal gain variat...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2013-04, Vol.48 (4), p.996-1008
Hauptverfasser:	Ferriss, M., Plouchart, J., Natarajan, A., Rylyakov, A., Parker, B., Tierno, J., Babakhani, A., Yaldiz, S., Valdes-Garcia, A., Sadhu, B., Friedman, D.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Bandwidth calibration Capacitors Charge pumps Circuit properties Circuits of signal characteristics conditioning (including delay circuits) Design. Technologies. Operation analysis. Testing Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology frequency synthesizers Integrated circuits Oscillators, resonators, synthetizers phase locked loop Phase locked loops Phase noise PLL Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Transfer functions Voltage-controlled oscillators
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Zusammenfassung:	An integral-path self-calibration scheme is introduced as part of a 20.1 GHz to 26.7 GHz low-noise PLL in 32 nm CMOS SOI. A dual-loop architecture in combination with an integral path measurement and correction scheme desensitizes the loop transfer function to the VCO's small signal gain variations. The spread of gain peaking is reduced by self-calibration from 2.4 dB to 1 dB, when measured at 70 sites on a 300 mm wafer. The PLL has a measured phase noise @10 MHz offset of -126.5 dBc/Hz at 20.1 GHz and - 124.2 dBc/Hz at 24 GHz
ISSN:	0018-9200 1558-173X
DOI:	10.1109/JSSC.2013.2239114