A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, Ultra Low Leakage Power Memory Using Dynamic Cell Stability and a Dual Swing Data Link

This paper presents the design of a high-speed ultra low power SRAM memory. Divided bit lines improve dynamic cell stability while at the same time decreasing active energy consumption. To limit unnecessary activity, word lines are divided on a word-by-word basis. Local write sense amplifiers make it possible to use low swing signaling on the global bit lines. To control this architecture, a distributed decoder is used. The use of dual swing data links on the global bit lines limits the impact of local write sense amplifier offset on the overall energy consumption. Using high threshold transistors in the memory cells reduces static power consumption and improves the cell's read stability. A partly dynamic decoder structure increases memory speed at a very low energy cost. The timing of this memory is made configurable to be able to cope with PVT variations without increasing design margins. The designed 256 kbit memory was fabricated in a 65 nm triple-V T process. It operates up to a speed of 850 MHz while only consuming 4.3 pJ/access for a word length of 32 bit. Standby leakage power is 25.2 W. This memory clearly outperforms other state-of-the-art designs when targeting high-speed, low-leakage and low active energy applications.