$A Sub- \mu s Wake-Up Time Power Gating Technique With Bypass Power Line for Rush Current Support$

A Sub- \mu s Wake-Up Time Power Gating Technique With Bypass Power Line for Rush Current Support

A sub-mus wake-up time power gating technique was developed for low-power SoCs. It uses two types of power switches and a separated power line bypassing rush current to suppress power-supply-voltage fluctuation. We applied this technique to a heterogeneous dual-core microprocessor fabricated in 90 n...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2009-04, Vol.44 (4), p.1178-1183
Hauptverfasser:	Kawasaki, K.-i., Shiota, T., Nakayama, K., Inoue, A.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Bypasses Circuits CMOS CMOS technology Data processing Delay Design. Technologies. Operation analysis. Testing Electric potential Electrical engineering. Electrical power engineering Electronic equipment and fabrication. Passive components, printed wiring boards, connectics Electronics Exact sciences and technology Fluctuation Gating and risering Integrated circuits Integrated circuits by function (including memories and processors) Leakage current Microprocessors Personal digital assistants Power electronics, power supplies Power gating Power lines rush current Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices standby leakage Switches Voltage Voltage fluctuations wake-up time
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