A 32-bit microprocessor for Smalltalk
SOAR (Smalltalk on a RISC), a 32-bit microprocessor designed for the efficient execution of compiled Smalltalk, is described. The chip, implemented in 4-/spl mu/m single-level metal NMOS technologies, has a cycle time of 400 ns. Pipelining allows an instruction to start each cycle with the exception...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 1986-10, Vol.21 (5), p.741-749 |
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| container_end_page | 749 |
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| container_issue | 5 |
| container_start_page | 741 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 21 |
| creator | Pendleton, J.M. Kong, S.I. Brown, E.W. Dunlap, F. Marino, C. Ungar, D.M. Patterson, D.A. Hodges, D.A. |
| description | SOAR (Smalltalk on a RISC), a 32-bit microprocessor designed for the efficient execution of compiled Smalltalk, is described. The chip, implemented in 4-/spl mu/m single-level metal NMOS technologies, has a cycle time of 400 ns. Pipelining allows an instruction to start each cycle with the exception of loads and stores. The processor contains 35700 transistors, is 320/spl times/432 mil, dissipates 3 W, and is assembled in an 84-lead pin grid array package. A design methodology that included a large CAD effort and provided functioning chips on first silicon was used. The SOAR hardware environment is a SUN workstation that includes a custom SOAR board and extra memory. |
| doi_str_mv | 10.1109/JSSC.1986.1052603 |
| format | Article |
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The chip, implemented in 4-/spl mu/m single-level metal NMOS technologies, has a cycle time of 400 ns. Pipelining allows an instruction to start each cycle with the exception of loads and stores. The processor contains 35700 transistors, is 320/spl times/432 mil, dissipates 3 W, and is assembled in an 84-lead pin grid array package. A design methodology that included a large CAD effort and provided functioning chips on first silicon was used. The SOAR hardware environment is a SUN workstation that includes a custom SOAR board and extra memory.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.1986.1052603</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Assembly ; Design automation ; Design methodology ; Electronics ; Electronics packaging ; Exact sciences and technology ; Hardware ; Integrated circuits ; Microprocessors ; MOS devices ; Pipeline processing ; Reduced instruction set computing ; Semiconductor electronics. Microelectronics. Optoelectronics. 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The chip, implemented in 4-/spl mu/m single-level metal NMOS technologies, has a cycle time of 400 ns. Pipelining allows an instruction to start each cycle with the exception of loads and stores. The processor contains 35700 transistors, is 320/spl times/432 mil, dissipates 3 W, and is assembled in an 84-lead pin grid array package. A design methodology that included a large CAD effort and provided functioning chips on first silicon was used. The SOAR hardware environment is a SUN workstation that includes a custom SOAR board and extra memory.</description><subject>Applied sciences</subject><subject>Assembly</subject><subject>Design automation</subject><subject>Design methodology</subject><subject>Electronics</subject><subject>Electronics packaging</subject><subject>Exact sciences and technology</subject><subject>Hardware</subject><subject>Integrated circuits</subject><subject>Microprocessors</subject><subject>MOS devices</subject><subject>Pipeline processing</subject><subject>Reduced instruction set computing</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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Microelectronics. Optoelectronics. Solid state devices</topic><topic>Silicon</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Pendleton, J.M.</creatorcontrib><creatorcontrib>Kong, S.I.</creatorcontrib><creatorcontrib>Brown, E.W.</creatorcontrib><creatorcontrib>Dunlap, F.</creatorcontrib><creatorcontrib>Marino, C.</creatorcontrib><creatorcontrib>Ungar, D.M.</creatorcontrib><creatorcontrib>Patterson, D.A.</creatorcontrib><creatorcontrib>Hodges, D.A.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Technology Research Database</collection><collection>Aerospace Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Electronics & Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Pendleton, J.M.</au><au>Kong, S.I.</au><au>Brown, E.W.</au><au>Dunlap, F.</au><au>Marino, C.</au><au>Ungar, D.M.</au><au>Patterson, D.A.</au><au>Hodges, D.A.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 32-bit microprocessor for Smalltalk</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1986-10-01</date><risdate>1986</risdate><volume>21</volume><issue>5</issue><spage>741</spage><epage>749</epage><pages>741-749</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>SOAR (Smalltalk on a RISC), a 32-bit microprocessor designed for the efficient execution of compiled Smalltalk, is described. The chip, implemented in 4-/spl mu/m single-level metal NMOS technologies, has a cycle time of 400 ns. Pipelining allows an instruction to start each cycle with the exception of loads and stores. The processor contains 35700 transistors, is 320/spl times/432 mil, dissipates 3 W, and is assembled in an 84-lead pin grid array package. A design methodology that included a large CAD effort and provided functioning chips on first silicon was used. The SOAR hardware environment is a SUN workstation that includes a custom SOAR board and extra memory.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/JSSC.1986.1052603</doi><tpages>9</tpages></addata></record> |
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| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 1986-10, Vol.21 (5), p.741-749 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_crossref_primary_10_1109_JSSC_1986_1052603 |
| source | IEEE Xplore |
| subjects | Applied sciences Assembly Design automation Design methodology Electronics Electronics packaging Exact sciences and technology Hardware Integrated circuits Microprocessors MOS devices Pipeline processing Reduced instruction set computing Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon |
| title | A 32-bit microprocessor for Smalltalk |
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