A 32-bit microprocessor for Smalltalk

A 32-bit microprocessor for Smalltalk

SOAR (Smalltalk on a RISC), a 32-bit microprocessor designed for the efficient execution of compiled Smalltalk, is described. The chip, implemented in 4-/spl mu/m single-level metal NMOS technologies, has a cycle time of 400 ns. Pipelining allows an instruction to start each cycle with the exception...

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Veröffentlicht in:IEEE journal of solid-state circuits 1986-10, Vol.21 (5), p.741-749
Hauptverfasser: Pendleton, J.M., Kong, S.I., Brown, E.W., Dunlap, F., Marino, C., Ungar, D.M., Patterson, D.A., Hodges, D.A.
Format: Artikel
Sprache:eng
Schlagworte:
Applied sciences
Assembly
Design automation
Design methodology
Electronics
Electronics packaging
Exact sciences and technology
Hardware
Integrated circuits
Microprocessors
MOS devices
Pipeline processing
Reduced instruction set computing
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Silicon
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Beschreibung
Zusammenfassung:SOAR (Smalltalk on a RISC), a 32-bit microprocessor designed for the efficient execution of compiled Smalltalk, is described. The chip, implemented in 4-/spl mu/m single-level metal NMOS technologies, has a cycle time of 400 ns. Pipelining allows an instruction to start each cycle with the exception of loads and stores. The processor contains 35700 transistors, is 320/spl times/432 mil, dissipates 3 W, and is assembled in an 84-lead pin grid array package. A design methodology that included a large CAD effort and provided functioning chips on first silicon was used. The SOAR hardware environment is a SUN workstation that includes a custom SOAR board and extra memory.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.1986.1052603