A Monolithic Amorphous-Selenium/CMOS Visible-Light Imager With Sub-9-μm Pixel Pitch and Extended Full-Well Capacity

We present a monolithic hybrid visible-light imager composed of an amorphous selenium (a-Se) photoconductor thin film integrated on a CMOS active pixel sensor (APS) array readout integrated circuit. We achieve more than 14-dB signal-to-noise ratio under monochromatic light at an illuminance of 0.04 lux in one quadrant of the imager containing 7.8\times 7.8-\mu \,\,\text{m}^{2} pixels using a 1.6-s exposure (integration) time without operating the a-Se sensor in avalanche mode. Long integration times are made possible by exploiting the low dark-current of a 20- \mu \text{m} -thick a-Se sensor layer and by implementing dark-current reduction techniques in the APS, such as series stacking reset and protection devices. In addition, use of a relatively thick 20- \mu \text{m} a-Se layer obviates the need for an additional planarization step of the sensing layer as was done with a previously-reported avalanche-mode a-Se/CMOS imager that incorporated a 0.5- \mu \text{m} -thick sensing layer. We also demonstrate an improved APS design, with 7.8\times 8.7-\mu \,\,\text{m}^{2} dimensions, containing a programmable in-pixel integration capacitor to provide enhanced full-well capacity (FWC) for a-Se/CMOS imagers. Measured results show that our APS achieves a FWC of approximately 230 ke − , which is comparable to several previously-reported photodiode-based CMOS imagers with extended FWC. Our imager can also resolve an effective object size of approximately 12.5~\mu \text{m} , demonstrated through measurement of the modulation transfer function.