Single Exciton Quantum Logic Circuits

We describe new logic devices based on the storage and shuttling of individual excitons, called the single exciton quantum (SEQ) logic. SEQ logic can implement memory, concatenation, fan-out, and gain. The logic circuits are based on quasi 1-D semiconductors that are coupled to quantum dots (QDs) an...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE journal of quantum electronics 2012-09, Vol.48 (9), p.1158-1164
1. Verfasser: Lee, Ji Ung
Format: Artikel
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:We describe new logic devices based on the storage and shuttling of individual excitons, called the single exciton quantum (SEQ) logic. SEQ logic can implement memory, concatenation, fan-out, and gain. The logic circuits are based on quasi 1-D semiconductors that are coupled to quantum dots (QDs) and on the engineering of their respective exciton states. The coding of binary states is based on the presence or absence of excitons in the QD, and the 1-D semiconductors serve as interconnects for shuttling excitons from one QD to another. Here, the QD serves as memory where the storage of excitonic excitations can be controlled electrically. Their transfer between 1-D semiconductors and QDs occurs through efficient nonradiative resonant energy transfer mechanisms. To allow low-power operations, the excitonic energy levels are cascaded to allow funneling of excitons where in the transfer of information is set to flow naturally in the direction of lower energy states. The principle of energy funnel, coupled with high drift velocity of excitons expected in 1-D semiconductors, allows low power, high speed logic circuits that can operate at room temperature. The use of excitons as a state-variable lends naturally to implementing optical interconnects for the input and output of an all-excitonic chip. Here, we describe the fundamental principles behind the proposed SEQ logic circuits, and describe the implementation of a universal nand logic.
ISSN:0018-9197
1558-1713
DOI:10.1109/JQE.2012.2205558