Modeling and Suppression of Zero-Sequence Circulating Current Resonance for Parallel Interleaved Inverters With Bypass Capacitor Based Leakage Current Mitigation

Connection of the neutral point of the ac capacitor to the midpoint or positive (negative) rail of the dc link is a cost-effective method to suppress the leakage current to ground. However, applying it to a modular parallel interleaved inverter system with the common ac and dc bus will induce zero-sequence circulating current (ZSCC) resonance issue. This paper firstly establishes the common mode equivalent circuit model of the multi-parallel inverters system. Secondly, the generation mechanism of ZSCC resonance is investigated based on the installed impedance model. To guarantee the stable operation, the resonance suppression method which combines the sampling instant shift and phase lag compensation is proposed. The frequency aliasing phenomenon and resultant ZSCC dc offset issue due to the sampling instant shift are further analyzed, and an effective suppression scheme of the ZSCC dc offset is proposed by adding an additional ZSCC dc offset control loop. Finally, the comparative experiments verify the effectiveness of the proposed method.