A Reduced Single-Phase Switched-Diode Cascaded Multilevel Inverter

The cascaded multilevel inverters (MLIs) are suitable topologies when a high number of voltage levels are needed. Nonetheless, cascaded topologies possess the main drawback of a high number of power switches and gate drivers that make sophisticated control, reducing efficiency, and increasing cost....

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Veröffentlicht in:IEEE journal of emerging and selected topics in power electronics 2021-06, Vol.9 (3), p.3556-3569
Hauptverfasser: Hosseinzadeh, Mohammad Ali, Sarebanzadeh, Maryam, Rivera, Marco, Babaei, Ebrahim, Wheeler, Patrick
Format: Artikel
Sprache:eng
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Zusammenfassung:The cascaded multilevel inverters (MLIs) are suitable topologies when a high number of voltage levels are needed. Nonetheless, cascaded topologies possess the main drawback of a high number of power switches and gate drivers that make sophisticated control, reducing efficiency, and increasing cost. This article proposes a new fundamental switched-diode topology that is capable of generating five positive-voltage levels with only three power switches, three power diodes, and three dc voltage sources. Based on a combination of the n number of new fundamental topology, two cascaded topologies are proposed, which increases the number of voltage levels and decreases the number of power switches and voltage stress. The proposed cascaded topologies can operate in asymmetric dc sources, so different dc voltage source magnitudes are submitted to minimize the number of components. The main advantages of the proposed cascaded topologies are reducing the number of power switches, and gate drivers with reasonable dc voltage sources count in comparison with other state-of-the-art cascaded topologies. Furthermore, the proposed topologies reduce the cost in comparison with other recent MLI topologies. The power loss analysis and the recommended application for the proposed topologies are discussed. The simulation and experimental works are presented to verify the operation correctness of the proposed topologies.
ISSN:2168-6777
2168-6785
DOI:10.1109/JESTPE.2020.3010793