Design and Implementation of an EMI-Immune Daisy Chain Interface With a PID-Based CDR Algorithm for Battery Management System Communication

Battery management systems (BMS) in electric vehicles (EVs) require robust communication interfaces to accurately monitor and control lithium-ion battery cells. The communication interface of daisy chain architecture has attracted more and more attention because of its lower deployment cost compared...

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Veröffentlicht in:IEEE access 2024, Vol.12, p.126438-126445
Hauptverfasser: Zheng, Zihan, Chen, Yongzhen, Ding, Jie, Xu, Xinhao, Deng, Kuan, Xiang, Yangxin, Li, Weibo, Wu, Jiangfeng
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Sprache:eng
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Zusammenfassung:Battery management systems (BMS) in electric vehicles (EVs) require robust communication interfaces to accurately monitor and control lithium-ion battery cells. The communication interface of daisy chain architecture has attracted more and more attention because of its lower deployment cost compared with the communication architecture of the controller area network (CAN). However, in automotive electronics, in order to meet safety standards, it is difficult to implement circuits that are highly robust to electromagnetic interference, which has also attracted many practitioners to study it. The problem of partial electromagnetic interference and clock jitter can be addressed not only by employing methods commonly used in the field of analog signals, but also by leveraging algorithms utilized in the domain of digital signals. This paper proposes an EMI-immune daisy chain interface circuit with a PID-based clock-data-recovery (CDR) algorithm, utilizing either a capacitor or a transformer as an isolator. The system includes a transmitter, an active receiver, a wake-up receiver, and the corresponding algorithm digital circuits, achieving a successful transmission under 39-dBm DPI injection. Simulation results demonstrate a CMTI of 100kV/ \mu s and low power consumption. The proposed CDR algorithm enables effective operation in the presence of clock frequency offset and EMI between chips. This paper thoroughly examines the underlying principles of the algorithm, supplemented by comprehensive test environments and accompanying data visuals.
ISSN:2169-3536
2169-3536
DOI:10.1109/ACCESS.2024.3429548