VLSI architectures for polygon recognition

A class of VLSI architectures is proposed for the computationally intensive task of polygon recognition in 3-D space. They make use of a set of local shape descriptors for polygons that are invariant under affine transformations. The recognition procedure is based on the matching of edge length rati...

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Veröffentlicht in:IEEE transactions on very large scale integration (VLSI) systems 1993-12, Vol.1 (4), p.398-407
Hauptverfasser: Sastry, R., Ranganathan, N., Bunke, H.
Format: Artikel
Sprache:eng
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Zusammenfassung:A class of VLSI architectures is proposed for the computationally intensive task of polygon recognition in 3-D space. They make use of a set of local shape descriptors for polygons that are invariant under affine transformations. The recognition procedure is based on the matching of edge length ratios using a simplified version of the dynamic programming procedure commonly used for string matching. The matching procedure also copes with partial occlusion of polygons. The architectures are systolic and fully utilize the principles of pipelining and parallelism in order to obtain high speed and throughput. A prototype VLSI chip implementing one of the proposed architectures is currently being built.< >
ISSN:1063-8210
1557-9999
DOI:10.1109/92.250186