Design and implementation of bandpass delta-sigma modulators using half-delay integrators

Design and implementation of bandpass delta-sigma modulators using half-delay integrators

Two bandpass delta-sigma A/D converters using half delay, integrators have been designed and implemented in a 2-/spl mu/m n-well double-poly double-metal CMOS process. The first design, a fourth-order architecture with an input modulation network, achieves a signal-to-noise ratio (SNR) of 73 dB over...

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Veröffentlicht in:IEEE transactions on circuits and systems. 2, Analog and digital signal processing Analog and digital signal processing, 1998-05, Vol.45 (5), p.535-546
Hauptverfasser: Chuang, S., Liu, H., Yu, X., Sculley, T.L., Bamberger, R.H.
Format: Artikel
Sprache:eng
Schlagworte:
Bandwidth
Circuit stability
Circuit synthesis
CMOS process
Computer science
Delta modulation
Linearity
Process design
Quantization
Signal design
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Beschreibung
Zusammenfassung:Two bandpass delta-sigma A/D converters using half delay, integrators have been designed and implemented in a 2-/spl mu/m n-well double-poly double-metal CMOS process. The first design, a fourth-order architecture with an input modulation network, achieves a signal-to-noise ratio (SNR) of 73 dB over a 0.005/spl pi/ input bandwidth, while the second design, a sixth-order topology, yielded a measured SNR of 80 dB over a 0.004/spl pi/ input bandwidth.
ISSN:1057-7130
1558-125X
DOI:10.1109/82.673635