The Grand Alliance system for US HDTV

The US HDTV process has fostered substantial research and development activity over the last several years. The Advisory Committee on Advanced Television Service (ACATS) was formed to advise the FCC on the technology and systems suitable for delivery of high definition service over terrestrial broad...

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Veröffentlicht in:Proceedings of the IEEE 1995-02, Vol.83 (2), p.158-174
Hauptverfasser: Challapali, K., Lebegue, X., Lim, J.S., Paik, W.H., Snopko, P.A.
Format: Artikel
Sprache:eng
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Zusammenfassung:The US HDTV process has fostered substantial research and development activity over the last several years. The Advisory Committee on Advanced Television Service (ACATS) was formed to advise the FCC on the technology and systems suitable for delivery of high definition service over terrestrial broadcast channels. Four digital HDTV systems where tested at the Advanced Television Testing Center. All the systems gave excellent performance, but the results were inconclusive and a plan for a second round of tests was prepared. As each of the four systems where being readied for retest. The proponents of the four individual digital HDTV proposals worked together to define a single HDTV system which incorporated the best technology from the individual systems. The consortium of companies, called the Grand Alliance (GA), announced a combined system and submitted it to ACATS for consideration. After ACATS certification, the GA began construction of a prototype system to submit for laboratory testing at the end of 1994. This paper describes the video compression subsystem and the hardware prototype. The preprocessing, motion estimation, quantization, and rate control subsystems are described. The system uses bidirectional motion compensation, discrete cosine transform, quantization and Huffman coding. The resulting bitstream is input into a transport system which uses fixed length packets. The multiplex transport stream is input into the 8-VSB transmission system. Finally, the specifics of the hardware implementation are described and some simulation results are presented.< >
ISSN:0018-9219
DOI:10.1109/5.364468