A 64-Mb DRAM with meshed power line

A 64-Mb DRAM with meshed power line

A 64-Mb dynamic RAM (DRAM) has been developed with a meshed power line (MPL) and a quasi-distributed sense-amplifier driver (qDSAD) scheme. It realizes high speed, t/sub RAS/=50 ns (typical) at V/sub cc/=3.3 V, and 16-b input/output (I/O). This MPL+qDSAD scheme can reduce sensing delay caused by the...

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Veröffentlicht in:IEEE journal of solid-state circuits 1991-11, Vol.26 (11), p.1506-1510
Hauptverfasser: Yamada, T., Nakata, Y., Hasegawa, J., Amano, N., Shibayama, A., Sasago, M., Matsuo, N., Yabu, T., Matsumoto, S., Okada, S., Inoue, M.
Format: Artikel
Sprache:eng
Schlagworte:
Capacitance
Circuit noise
CMOS technology
Crosstalk
Degradation
Delay
Integrated circuit interconnections
Laser noise
Random access memory
Wiring
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Zusammenfassung:A 64-Mb dynamic RAM (DRAM) has been developed with a meshed power line (MPL) and a quasi-distributed sense-amplifier driver (qDSAD) scheme. It realizes high speed, t/sub RAS/=50 ns (typical) at V/sub cc/=3.3 V, and 16-b input/output (I/O). This MPL+qDSAD scheme can reduce sensing delay caused by the metal layer resistance. Furthermore, to suppress crosstalk noise, a V/sub SS/ shield peripheral layout scheme has been introduced, which also widens power line widths. This 64-Mb DRAM was fabricated with 0.4- mu m CMOS technology using KrF excimer laser lithography. A newly developed memory cell structure, the tunnel-shaped stacked-capacitor cell (TSSC), was adapted to this 64-Mb DRAM.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.98965