A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme

A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme

A 1.8-V-only 32-Mb NOR flash EEPROM has been developed based on the 0.25-/spl mu/m triple-well double-metal CMOS process. A channel-erasing scheme has been implemented to realize a cell size of 0.49 /spl mu/m/sup 2/, the smallest yet reported for 0.25-/spl mu/m CMOS technology. A block decoder circu...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE journal of solid-state circuits 2000-11, Vol.35 (11), p.1648-1654
Hauptverfasser: Atsumi, S., Umezawa, A., Tanzawa, T., Taura, T., Shiga, H., Takano, Y., Miyaba, T., Matsui, M., Watanabe, H., Isobe, K., Kitamura, S., Yamada, S., Saito, M., Mori, S., Watanabe, T.
Format: Artikel
Sprache:eng
Schlagworte:
Blocking
Circuits
CMOS
CMOS technology
Decoding
Detection
EEPROM
Electric potential
Energy consumption
EPROM
Flash memory
High speed
Large scale integration
Substrates
Tunneling
Voltage
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A 1.8-V-only 32-Mb NOR flash EEPROM has been developed based on the 0.25-/spl mu/m triple-well double-metal CMOS process. A channel-erasing scheme has been implemented to realize a cell size of 0.49 /spl mu/m/sup 2/, the smallest yet reported for 0.25-/spl mu/m CMOS technology. A block decoder circuit with a novel erase-reset sequence has been designed for the channel-erasing operation. A bitline direct sensing scheme and a wordline boosted voltage pooling method have been developed to obtain high-speed reading operation at low voltage. An access time of 90 ns at 1.8 V has been realized.
ISSN:0018-9200
1558-173X
DOI:10.1109/4.881211