Multilevel optimization in the design of a high-performance GaAs microcomputer
Multilevel optimization in the design of an instruction cache for a high-performance GaAs microprocessor is discussed. The performance of the system is maximized by concurrently considering the interrelationships of (1) the time of flight of signals across the multichip module on which the processor...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 1991-05, Vol.26 (5), p.763-767 |
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| container_end_page | 767 |
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| container_title | IEEE journal of solid-state circuits |
| container_volume | 26 |
| creator | Olukotun, O.A. Brown, R.B. Lomax, R.J. Mudge, T.N. Sakallah, K.A. |
| description | Multilevel optimization in the design of an instruction cache for a high-performance GaAs microprocessor is discussed. The performance of the system is maximized by concurrently considering the interrelationships of (1) the time of flight of signals across the multichip module on which the processor and cache chips are mounted, (2) the clocking scheme that synchronizes these signals, and (3) the size of the cache. These three design issues are normally considered independently because they arise in different abstraction levels. Design automation tools developed to facilitate this multilevel optimization are described. This process, applied to various subsystems, has been used to gain substantial performance improvement in the GaAs microcomputer.< > |
| doi_str_mv | 10.1109/4.78246 |
| format | Article |
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The performance of the system is maximized by concurrently considering the interrelationships of (1) the time of flight of signals across the multichip module on which the processor and cache chips are mounted, (2) the clocking scheme that synchronizes these signals, and (3) the size of the cache. These three design issues are normally considered independently because they arise in different abstraction levels. Design automation tools developed to facilitate this multilevel optimization are described. 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The performance of the system is maximized by concurrently considering the interrelationships of (1) the time of flight of signals across the multichip module on which the processor and cache chips are mounted, (2) the clocking scheme that synchronizes these signals, and (3) the size of the cache. These three design issues are normally considered independently because they arise in different abstraction levels. Design automation tools developed to facilitate this multilevel optimization are described. This process, applied to various subsystems, has been used to gain substantial performance improvement in the GaAs microcomputer.< ></description><subject>Applied sciences</subject><subject>Clocks</subject><subject>Design automation</subject><subject>Design optimization</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Gallium arsenide</subject><subject>Microcomputers</subject><subject>Microprocessors</subject><subject>Multichip modules</subject><subject>Performance gain</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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Microelectronics. Optoelectronics. Solid state devices</topic><topic>Signal processing</topic><topic>Synchronization</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Olukotun, O.A.</creatorcontrib><creatorcontrib>Brown, R.B.</creatorcontrib><creatorcontrib>Lomax, R.J.</creatorcontrib><creatorcontrib>Mudge, T.N.</creatorcontrib><creatorcontrib>Sakallah, K.A.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Technology Research Database</collection><collection>Aerospace Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Electronics & Communications Abstracts</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Olukotun, O.A.</au><au>Brown, R.B.</au><au>Lomax, R.J.</au><au>Mudge, T.N.</au><au>Sakallah, K.A.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Multilevel optimization in the design of a high-performance GaAs microcomputer</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1991-05-01</date><risdate>1991</risdate><volume>26</volume><issue>5</issue><spage>763</spage><epage>767</epage><pages>763-767</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>Multilevel optimization in the design of an instruction cache for a high-performance GaAs microprocessor is discussed. The performance of the system is maximized by concurrently considering the interrelationships of (1) the time of flight of signals across the multichip module on which the processor and cache chips are mounted, (2) the clocking scheme that synchronizes these signals, and (3) the size of the cache. These three design issues are normally considered independently because they arise in different abstraction levels. Design automation tools developed to facilitate this multilevel optimization are described. This process, applied to various subsystems, has been used to gain substantial performance improvement in the GaAs microcomputer.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/4.78246</doi><tpages>5</tpages></addata></record> |
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| ispartof | IEEE journal of solid-state circuits, 1991-05, Vol.26 (5), p.763-767 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_crossref_primary_10_1109_4_78246 |
| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Clocks Design automation Design optimization Electronics Exact sciences and technology Gallium arsenide Microcomputers Microprocessors Multichip modules Performance gain Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal processing Synchronization |
| title | Multilevel optimization in the design of a high-performance GaAs microcomputer |
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