Multilevel optimization in the design of a high-performance GaAs microcomputer

Multilevel optimization in the design of an instruction cache for a high-performance GaAs microprocessor is discussed. The performance of the system is maximized by concurrently considering the interrelationships of (1) the time of flight of signals across the multichip module on which the processor...

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Veröffentlicht in:IEEE journal of solid-state circuits 1991-05, Vol.26 (5), p.763-767
Hauptverfasser: Olukotun, O.A., Brown, R.B., Lomax, R.J., Mudge, T.N., Sakallah, K.A.
Format: Artikel
Sprache:eng
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Zusammenfassung:Multilevel optimization in the design of an instruction cache for a high-performance GaAs microprocessor is discussed. The performance of the system is maximized by concurrently considering the interrelationships of (1) the time of flight of signals across the multichip module on which the processor and cache chips are mounted, (2) the clocking scheme that synchronizes these signals, and (3) the size of the cache. These three design issues are normally considered independently because they arise in different abstraction levels. Design automation tools developed to facilitate this multilevel optimization are described. This process, applied to various subsystems, has been used to gain substantial performance improvement in the GaAs microcomputer.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.78246