A portable digital DLL for high-speed CMOS interface circuits
A digital delay-locked loop (DLL) that achieves infinite phase range and 40-ps worst case phase resolution at 400 MHz was developed in a 3.3-V, 0.4-/spl mu/m standard CMOS process. The DLL uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correcting multiplexers. Th...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 1999-05, Vol.34 (5), p.632-644 |
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| container_end_page | 644 |
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| container_issue | 5 |
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| container_title | IEEE journal of solid-state circuits |
| container_volume | 34 |
| creator | Garlepp, B.W. Donnelly, K.S. Jun Kim Chau, P.S. Zerbe, J.L. Huang, C. Tran, C.V. Portmann, C.L. Stark, D. Yiu-Fai Chan Lee, T.H. Horowitz, M.A. |
| description | A digital delay-locked loop (DLL) that achieves infinite phase range and 40-ps worst case phase resolution at 400 MHz was developed in a 3.3-V, 0.4-/spl mu/m standard CMOS process. The DLL uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correcting multiplexers. This more easily process portable DLL achieves jitter performance comparable to a more complex analog DLL when placed into identical high-speed interface circuits fabricated on the same test-chip die. At 400 MHz, the digital DLL provides |
| doi_str_mv | 10.1109/4.760373 |
| format | Article |
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The DLL occupies 0.96 mm/sup 2/.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/4.760373</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>IEEE</publisher><subject>Associate members ; Blenders ; Circuit testing ; Circuits ; Clocks ; CMOS ; CMOS digital integrated circuits ; CMOS process ; Delay lines ; Digital ; Dynamic link libraries ; High speed ; Jitter ; Phase detection ; Portability ; Standards development ; Voltage</subject><ispartof>IEEE journal of solid-state circuits, 1999-05, Vol.34 (5), p.632-644</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c339t-acb7320dc48bec253fb5880190d59ea02288baeacdc52a0841b47039570b475a3</citedby><cites>FETCH-LOGICAL-c339t-acb7320dc48bec253fb5880190d59ea02288baeacdc52a0841b47039570b475a3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/760373$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/760373$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Garlepp, B.W.</creatorcontrib><creatorcontrib>Donnelly, K.S.</creatorcontrib><creatorcontrib>Jun Kim</creatorcontrib><creatorcontrib>Chau, P.S.</creatorcontrib><creatorcontrib>Zerbe, J.L.</creatorcontrib><creatorcontrib>Huang, C.</creatorcontrib><creatorcontrib>Tran, C.V.</creatorcontrib><creatorcontrib>Portmann, C.L.</creatorcontrib><creatorcontrib>Stark, D.</creatorcontrib><creatorcontrib>Yiu-Fai Chan</creatorcontrib><creatorcontrib>Lee, T.H.</creatorcontrib><creatorcontrib>Horowitz, M.A.</creatorcontrib><title>A portable digital DLL for high-speed CMOS interface circuits</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>A digital delay-locked loop (DLL) that achieves infinite phase range and 40-ps worst case phase resolution at 400 MHz was developed in a 3.3-V, 0.4-/spl mu/m standard CMOS process. The DLL uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correcting multiplexers. This more easily process portable DLL achieves jitter performance comparable to a more complex analog DLL when placed into identical high-speed interface circuits fabricated on the same test-chip die. At 400 MHz, the digital DLL provides <250 ps peak-to-peak long-term jitter at 3.3 V and operates down to 1.7 V, where it dissipates 60 mW. The DLL occupies 0.96 mm/sup 2/.</description><subject>Associate members</subject><subject>Blenders</subject><subject>Circuit testing</subject><subject>Circuits</subject><subject>Clocks</subject><subject>CMOS</subject><subject>CMOS digital integrated circuits</subject><subject>CMOS process</subject><subject>Delay lines</subject><subject>Digital</subject><subject>Dynamic link libraries</subject><subject>High speed</subject><subject>Jitter</subject><subject>Phase detection</subject><subject>Portability</subject><subject>Standards development</subject><subject>Voltage</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1999</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqF0D1PwzAQBmALgUQpSMxMnhBLyvmrtgcGVD6loA6AxBY5zqU1SptgpwP_nqBWsMF0d3of3fAScspgwhjYSznRUxBa7JERU8pkTIu3fTICYCazHOCQHKX0PpxSGjYiV9e0a2PvygZpFRahdw29yXNat5Euw2KZpQ6xorOn-TMN6x5j7TxSH6LfhD4dk4PaNQlPdnNMXu9uX2YPWT6_f5xd55kXwvaZ86UWHCovTYmeK1GXyhhgFipl0QHnxpQOna-84g6MZKXUIKzSMCzKiTE53_7tYvuxwdQXq5A8No1bY7tJBTeK2ynI_6EGO-VaDPDiT8immnFlQLJf6mObUsS66GJYufhZMCi-Oy9kse18oGdbGhDxh-3CL8iEeSU</recordid><startdate>19990501</startdate><enddate>19990501</enddate><creator>Garlepp, B.W.</creator><creator>Donnelly, K.S.</creator><creator>Jun Kim</creator><creator>Chau, P.S.</creator><creator>Zerbe, J.L.</creator><creator>Huang, C.</creator><creator>Tran, C.V.</creator><creator>Portmann, C.L.</creator><creator>Stark, D.</creator><creator>Yiu-Fai Chan</creator><creator>Lee, T.H.</creator><creator>Horowitz, M.A.</creator><general>IEEE</general><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>F28</scope><scope>FR3</scope><scope>L7M</scope><scope>7SC</scope><scope>JQ2</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>19990501</creationdate><title>A portable digital DLL for high-speed CMOS interface circuits</title><author>Garlepp, B.W. ; Donnelly, K.S. ; Jun Kim ; Chau, P.S. ; Zerbe, J.L. ; Huang, C. ; Tran, C.V. ; Portmann, C.L. ; Stark, D. ; Yiu-Fai Chan ; Lee, T.H. ; Horowitz, M.A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c339t-acb7320dc48bec253fb5880190d59ea02288baeacdc52a0841b47039570b475a3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1999</creationdate><topic>Associate members</topic><topic>Blenders</topic><topic>Circuit testing</topic><topic>Circuits</topic><topic>Clocks</topic><topic>CMOS</topic><topic>CMOS digital integrated circuits</topic><topic>CMOS process</topic><topic>Delay lines</topic><topic>Digital</topic><topic>Dynamic link libraries</topic><topic>High speed</topic><topic>Jitter</topic><topic>Phase detection</topic><topic>Portability</topic><topic>Standards development</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Garlepp, B.W.</creatorcontrib><creatorcontrib>Donnelly, K.S.</creatorcontrib><creatorcontrib>Jun Kim</creatorcontrib><creatorcontrib>Chau, P.S.</creatorcontrib><creatorcontrib>Zerbe, J.L.</creatorcontrib><creatorcontrib>Huang, C.</creatorcontrib><creatorcontrib>Tran, C.V.</creatorcontrib><creatorcontrib>Portmann, C.L.</creatorcontrib><creatorcontrib>Stark, D.</creatorcontrib><creatorcontrib>Yiu-Fai Chan</creatorcontrib><creatorcontrib>Lee, T.H.</creatorcontrib><creatorcontrib>Horowitz, M.A.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts</collection><collection>ProQuest Computer Science Collection</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Garlepp, B.W.</au><au>Donnelly, K.S.</au><au>Jun Kim</au><au>Chau, P.S.</au><au>Zerbe, J.L.</au><au>Huang, C.</au><au>Tran, C.V.</au><au>Portmann, C.L.</au><au>Stark, D.</au><au>Yiu-Fai Chan</au><au>Lee, T.H.</au><au>Horowitz, M.A.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A portable digital DLL for high-speed CMOS interface circuits</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1999-05-01</date><risdate>1999</risdate><volume>34</volume><issue>5</issue><spage>632</spage><epage>644</epage><pages>632-644</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>A digital delay-locked loop (DLL) that achieves infinite phase range and 40-ps worst case phase resolution at 400 MHz was developed in a 3.3-V, 0.4-/spl mu/m standard CMOS process. The DLL uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correcting multiplexers. This more easily process portable DLL achieves jitter performance comparable to a more complex analog DLL when placed into identical high-speed interface circuits fabricated on the same test-chip die. At 400 MHz, the digital DLL provides <250 ps peak-to-peak long-term jitter at 3.3 V and operates down to 1.7 V, where it dissipates 60 mW. The DLL occupies 0.96 mm/sup 2/.</abstract><pub>IEEE</pub><doi>10.1109/4.760373</doi><tpages>13</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) |
| subjects | Associate members Blenders Circuit testing Circuits Clocks CMOS CMOS digital integrated circuits CMOS process Delay lines Digital Dynamic link libraries High speed Jitter Phase detection Portability Standards development Voltage |
| title | A portable digital DLL for high-speed CMOS interface circuits |
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