A 23-ns 1-Mb BiCMOS DRAM

A 23-ns 1-Mb BiCMOS DRAM

A 1-Mb BiCMOS DRAM having a 23-ns access time is described. The DRAM uses a direct sensing technique and a nonaddress-multiplexing configuration. This technique combines the NMOS differential circuit on each pair of data lines with a common highly sensitive bipolar circuit. The resulting chip has be...

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Veröffentlicht in:IEEE journal of solid-state circuits 1990-10, Vol.25 (5), p.1102-1111
Hauptverfasser: Kitsukawa, G., Yanagisawa, K., Kobayashi, Y., Kinoshita, Y., Ohta, T., Udagawa, T., Miwa, H., Miyazawa, H., Kawajiri, Y., Ouchi, Y., Tsukada, H., Matsumoto, T., Itoh, K.
Format: Artikel
Sprache:eng
Schlagworte:
Application software
Applied sciences
BiCMOS integrated circuits
Driver circuits
Electronics
Exact sciences and technology
Integrated circuits
Integrated circuits by function (including memories and processors)
Laboratories
Lithography
Microprocessors
MOS devices
Random access memory
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Timing
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Zusammenfassung:A 1-Mb BiCMOS DRAM having a 23-ns access time is described. The DRAM uses a direct sensing technique and a nonaddress-multiplexing configuration. This technique combines the NMOS differential circuit on each pair of data lines with a common highly sensitive bipolar circuit. The resulting chip has been verified to have high-speed characteristics while maintaining a wide operating margin and a relatively small chip size of 62.2 mm/sup 2/, in spite of a 1.3- mu m lithography level.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.62130