A VLSI chip set for a multiprocessor workstation. I. An RISC microprocessor with coprocessor interface and support for symbolic processing

A VLSI chip set for a multiprocessor workstation. I. An RISC microprocessor with coprocessor interface and support for symbolic processing

A 40-70 MIPS multiprocessor workstation is considered. VLSI implementation of the central processing unit (CPU) chip, based on reduced instruction set computer (RISC) architecture and with support for LISP, is described. The 1.3-cm/sup 2/ CPU chip uses a direct-mapped 512-b on-chip instruction cache...

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Veröffentlicht in:IEEE journal of solid-state circuits 1989-12, Vol.24 (6), p.1688-1698
Hauptverfasser: Lee, D.D., Kong, S.I., Hill, M.D., Taylor, G.S., Hodges, D.A., Katz, R.H., Patterson, D.A.
Format: Artikel
Sprache:eng
Schlagworte:
Applied sciences
Central Processing Unit
Clocks
CMOS technology
Computers, microcomputers
Coprocessors
Electronics
Exact sciences and technology
Hardware
Memory management
Microprocessors
Reduced instruction set computing
Very large scale integration
Workstations
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Zusammenfassung:A 40-70 MIPS multiprocessor workstation is considered. VLSI implementation of the central processing unit (CPU) chip, based on reduced instruction set computer (RISC) architecture and with support for LISP, is described. The 1.3-cm/sup 2/ CPU chip uses a direct-mapped 512-b on-chip instruction cache and 138 40-b registers organized in eight overlapping windows to achieve 10 MIPS per processor peak performance with a 10-MHz, four-phase clock.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.45007