A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers

A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers

A 4-Mb CMOS SRAM with 3.84 /spl mu/m/sup 2/ TFT load cells is fabricated using 0.25-/spl mu/m CMOS technology and achieves an address access time of 6 ns at a supply voltage of 2.7 V. The use of a current sense amplifier that is insensitive to its offset voltage enables the fast access time. A boost...

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Veröffentlicht in:IEEE journal of solid-state circuits 1995-04, Vol.30 (4), p.480-486
Hauptverfasser: Ishibashi, K., Takasugi, K., Komiyaji, K., Toyoshima, H., Yamanaka, T., Fukami, A., Hashimoto, N., Ohki, N., Shimizu, A., Hashimoto, T., Nagano, T., Nishida, T.
Format: Artikel
Sprache:eng
Schlagworte:
Applied sciences
Batteries
CMOS technology
Differential amplifiers
Electronics
Exact sciences and technology
Integrated circuits
Integrated circuits by function (including memories and processors)
Low voltage
Operational amplifiers
Personal digital assistants
Power dissipation
Random access memory
Reduced instruction set computing
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Thin film transistors
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Zusammenfassung:A 4-Mb CMOS SRAM with 3.84 /spl mu/m/sup 2/ TFT load cells is fabricated using 0.25-/spl mu/m CMOS technology and achieves an address access time of 6 ns at a supply voltage of 2.7 V. The use of a current sense amplifier that is insensitive to its offset voltage enables the fast access time. A boosted cell array architecture allows low voltage operation of fast SRAM's using TFT load cells.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.375969