S/370 sign-magnitude floating-point adder

S/370 sign-magnitude floating-point adder

A 56 bit S/370 sign-magnitude adder for floating-point operations implemented in a four-level metal bipolar master-slice technology is described. The design of the two-to-one adder is based on a carry lookahead scheme with implicit calculation of the end-around carry. The implementation of the float...

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Veröffentlicht in:IEEE journal of solid-state circuits 1989-08, Vol.24 (4), p.1062-1070
Hauptverfasser: Vassiliadis, S., Lemon, D.S., Putrino, M.
Format: Artikel
Sprache:eng
Schlagworte:
Algorithm design and analysis
Automatic logic units
Ceramics
Fault detection
Registers
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Zusammenfassung:A 56 bit S/370 sign-magnitude adder for floating-point operations implemented in a four-level metal bipolar master-slice technology is described. The design of the two-to-one adder is based on a carry lookahead scheme with implicit calculation of the end-around carry. The implementation of the floating-point adder and the error-detecting logic requires one chip of 7500 automatically placed and wired NAND gates. The chip die size is 7.39*7.39 mm/sup 2/, and it is mounted on a metallized ceramic substrate. The floating-point sign-magnitude adder chip is used in the IBM 9370 Model 60 (9375) engineering scientific accelerator card.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.34093