A 14 ns 256 K1 CMOS SRAM with multiple test modes

A 14 ns 256 K1 CMOS SRAM with multiple test modes

A methodology to enter and exit from test modes in asynchronous static RAMs (SRAMs) is presented. This chip is fabricated in a 0.7 mu m twin-tub, single-poly, double-metal technology on p/p/sup +/ epitaxial substrate. To prevent hot-electron degradation, a voltage regulator is used in the memory mat...

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Veröffentlicht in:IEEE journal of solid-state circuits 1989-08, Vol.24 (4), p.874-880
Hauptverfasser: Voss, P.H., Pfennings, L.C.M.G., Phelan, C.G., O'Connell, C.M., Davies, T.J., Ontrop, H., Bell, S.A., Salters, R.H.W.
Format: Artikel
Sprache:eng
Schlagworte:
Circuit testing
Degradation
Laboratories
Low earth orbit satellites
Matrix converters
Packaging
Random access memory
Switches
Timing
Voltage
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Beschreibung
Zusammenfassung:A methodology to enter and exit from test modes in asynchronous static RAMs (SRAMs) is presented. This chip is fabricated in a 0.7 mu m twin-tub, single-poly, double-metal technology on p/p/sup +/ epitaxial substrate. To prevent hot-electron degradation, a voltage regulator is used in the memory matrix, with the cascoding technique applied in the periphery. Circuits were implemented against voltage bumps and data glitching on the output. A small cell size of 5.1*13.7 mu m/sup 2/ and a chip size of 3.9*9.5 mm/sup 2/ have been achieved.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.34064