The use of stabilized CMOS delay lines for the digitization of short time intervals

The use of stabilized CMOS delay lines for the digitization of short time intervals

The basic advantages and limitations of using integrated digital CMOS delay lines for the digitization of short time intervals are discussed. Accuracies of 6-7 b and single-shot resolutions from 0.1 to 10 ns are demonstrated to be realizable using fully integrated, tapped, and voltage-controlled CMO...

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Veröffentlicht in:IEEE journal of solid-state circuits 1993-08, Vol.28 (8), p.887-894
Hauptverfasser: Rahkonen, T.E., Kostamovaara, J.T.
Format: Artikel
Sprache:eng
Schlagworte:
Applied sciences
Circuit properties
Circuits of signal characteristics conditioning (including delay circuits)
Clocks
CMOS logic circuits
Delay effects
Delay lines
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Flip-flops
Frequency
Interpolation
Pulse measurements
Time measurement
Timing
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Zusammenfassung:The basic advantages and limitations of using integrated digital CMOS delay lines for the digitization of short time intervals are discussed. Accuracies of 6-7 b and single-shot resolutions from 0.1 to 10 ns are demonstrated to be realizable using fully integrated, tapped, and voltage-controlled CMOS delay lines as a time base for the measurement.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.231325