A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

A 64-Mb dynamic random access memory (DRAM) with a 30-ns access time and 19.48-mm*9.55-mm die size has been developed. For reducing inter-bit-line coupling noise, the DRAM features a latched-sense, shared-sense circuit with open bit-line readout and folded bit-line rewrite operations. To reduce test...

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Veröffentlicht in:IEEE journal of solid-state circuits 1992-11, Vol.27 (11), p.1525-1533
Hauptverfasser: Tanabe, A., Takeshima, T., Koike, H., Aimoto, Y., Takada, M., Ishijima, T., Kasai, N., Hada, H., Shibahara, K., Kunio, T., Tanigawa, T., Saeki, T., Sakao, M., Miyamoto, H., Nozue, H., Ohya, S., Murotani, T., Koyama, K., Okuda, T.
Format: Artikel
Sprache:eng
Schlagworte:
Automatic testing
Built-in self-test
Circuit noise
Circuit testing
Coupling circuits
Error correction codes
Noise level
Noise reduction
Random access memory
Voltage
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Beschreibung
Zusammenfassung:A 64-Mb dynamic random access memory (DRAM) with a 30-ns access time and 19.48-mm*9.55-mm die size has been developed. For reducing inter-bit-line coupling noise, the DRAM features a latched-sense, shared-sense circuit with open bit-line readout and folded bit-line rewrite operations. To reduce test costs and increase chip reliability, it has been equipped with built-in self-test and self-repair (BIST and BISR) circuits that use spare SRAM cells.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.165332