A deterministic algorithm for automatic CMOS transistor sizing

A deterministic algorithm for automatic CMOS transistor sizing

A model which offers a closed-form equation for determining device size, based on speed and load, has been developed. The need for circuit simulation is eliminated in most cases. This model is used in a system for automatically producing performance-tuned cell layouts.< >

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Bibliographische Detailangaben
Veröffentlicht in:IEEE journal of solid-state circuits 1988-04, Vol.23 (2), p.522-526
Hauptverfasser: Richman, B.A., Hansen, J.E., Cameron, K.
Format: Artikel
Sprache:eng
Schlagworte:
Circuit simulation
Equations
Semiconductor device modeling
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Beschreibung
Zusammenfassung:A model which offers a closed-form equation for determining device size, based on speed and load, has been developed. The need for circuit simulation is eliminated in most cases. This model is used in a system for automatically producing performance-tuned cell layouts.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.1017