A 40-ps high electron mobility transistor 4.1 K gate array

A high-electron mobility transistor (HEMT) 4.1 K-gate array has been developed, using a selective dry etching process and a MBE (molecular-beam epitaxy) growth technology. The circuit design uses direct-coupled FET logic (DCFL). The chip contains 4096 NOR gates, each with a 0.8- mu m gate length, an...

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Veröffentlicht in:	IEEE journal of solid-state circuits 1988-04, Vol.23 (2), p.485-489
Hauptverfasser:	Kajii, K., Watanabe, Y., Suzuki, M., Hanyu, I., Kosugi, M., Odani, K., Mimura, T., Abe, M.
Format:	Artikel
Sprache:	eng
Schlagworte:	Circuit synthesis Dry etching FETs HEMTs Length measurement Logic circuits Logic design MODFETs Molecular beam epitaxial growth Semiconductor device measurement
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container_end_page	489
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container_title	IEEE journal of solid-state circuits
container_volume	23
creator	Kajii, K. Watanabe, Y. Suzuki, M. Hanyu, I. Kosugi, M. Odani, K. Mimura, T. Abe, M.
description	A high-electron mobility transistor (HEMT) 4.1 K-gate array has been developed, using a selective dry etching process and a MBE (molecular-beam epitaxy) growth technology. The circuit design uses direct-coupled FET logic (DCFL). The chip contains 4096 NOR gates, each with a 0.8- mu m gate length, and measures 6.3 mm4.8 mm. A basic gate delay of 40 ps has been achieved. A 1616-bit parallel multiplier, used to test this array, has a multiplication time of 4.1 ns at 300 K, where the power dissipation is 6.2 W.< >
doi_str_mv	10.1109/4.1011
format	Article
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The circuit design uses direct-coupled FET logic (DCFL). The chip contains 4096 NOR gates, each with a 0.8- mu m gate length, and measures 6.3 mm4.8 mm. A basic gate delay of 40 ps has been achieved. A 1616-bit parallel multiplier, used to test this array, has a multiplication time of 4.1 ns at 300 K, where the power dissipation is 6.2 W.< ></description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/4.1011</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit synthesis ; Dry etching ; FETs ; HEMTs ; Length measurement ; Logic circuits ; Logic design ; MODFETs ; Molecular beam epitaxial growth ; Semiconductor device measurement</subject><ispartof>IEEE journal of solid-state circuits, 1988-04, Vol.23 (2), p.485-489</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c232t-f6eb7b1f2eeadc7fcc61c7a0f0981a6f18c1fd30a0809b41c3083379baa9c10c3</citedby><cites>FETCH-LOGICAL-c232t-f6eb7b1f2eeadc7fcc61c7a0f0981a6f18c1fd30a0809b41c3083379baa9c10c3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1011$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1011$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Kajii, K.</creatorcontrib><creatorcontrib>Watanabe, Y.</creatorcontrib><creatorcontrib>Suzuki, M.</creatorcontrib><creatorcontrib>Hanyu, I.</creatorcontrib><creatorcontrib>Kosugi, M.</creatorcontrib><creatorcontrib>Odani, K.</creatorcontrib><creatorcontrib>Mimura, T.</creatorcontrib><creatorcontrib>Abe, M.</creatorcontrib><title>A 40-ps high electron mobility transistor 4.1 K gate array</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>A high-electron mobility transistor (HEMT) 4.1 K-gate array has been developed, using a selective dry etching process and a MBE (molecular-beam epitaxy) growth technology. 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A 1616-bit parallel multiplier, used to test this array, has a multiplication time of 4.1 ns at 300 K, where the power dissipation is 6.2 W.< ></description><subject>Circuit synthesis</subject><subject>Dry etching</subject><subject>FETs</subject><subject>HEMTs</subject><subject>Length measurement</subject><subject>Logic circuits</subject><subject>Logic design</subject><subject>MODFETs</subject><subject>Molecular beam epitaxial growth</subject><subject>Semiconductor device measurement</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1988</creationdate><recordtype>article</recordtype><recordid>eNqN0M1LAzEQBfAgCtaqZ485eds6k2ybxFspfmHBi4K3kE0nbWTbrUk89L93SwU9ehoe8-MdHmOXCCNEMDf1CAHxiA1wPNYVKvl-zAYAqCsjAE7ZWc4ffaxrjQN2O-U1VNvMV3G54tSSL6nb8HXXxDaWHS_JbXLMpUu87-XPfOkKcZeS252zk-DaTBc_d8je7u9eZ4_V_OXhaTadV15IUaowoUY1GASRW3gVvJ-gVw4CGI1uElB7DAsJDjSYpkYvQUupTOOc8QheDtn1oXebus8vysWuY_bUtm5D3Ve2QmsFKMb_gKgEKPMLfepyThTsNsW1SzuLYPcb2truN-zh1QFGIvqD-tc3oFBpVg</recordid><startdate>198804</startdate><enddate>198804</enddate><creator>Kajii, K.</creator><creator>Watanabe, Y.</creator><creator>Suzuki, M.</creator><creator>Hanyu, I.</creator><creator>Kosugi, M.</creator><creator>Odani, K.</creator><creator>Mimura, T.</creator><creator>Abe, M.</creator><general>IEEE</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>7U5</scope></search><sort><creationdate>198804</creationdate><title>A 40-ps high electron mobility transistor 4.1 K gate array</title><author>Kajii, K. ; Watanabe, Y. ; Suzuki, M. ; Hanyu, I. ; Kosugi, M. ; Odani, K. ; Mimura, T. ; Abe, M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c232t-f6eb7b1f2eeadc7fcc61c7a0f0981a6f18c1fd30a0809b41c3083379baa9c10c3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1988</creationdate><topic>Circuit synthesis</topic><topic>Dry etching</topic><topic>FETs</topic><topic>HEMTs</topic><topic>Length measurement</topic><topic>Logic circuits</topic><topic>Logic design</topic><topic>MODFETs</topic><topic>Molecular beam epitaxial growth</topic><topic>Semiconductor device measurement</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Kajii, K.</creatorcontrib><creatorcontrib>Watanabe, Y.</creatorcontrib><creatorcontrib>Suzuki, M.</creatorcontrib><creatorcontrib>Hanyu, I.</creatorcontrib><creatorcontrib>Kosugi, M.</creatorcontrib><creatorcontrib>Odani, K.</creatorcontrib><creatorcontrib>Mimura, T.</creatorcontrib><creatorcontrib>Abe, M.</creatorcontrib><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Solid State and Superconductivity Abstracts</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kajii, K.</au><au>Watanabe, Y.</au><au>Suzuki, M.</au><au>Hanyu, I.</au><au>Kosugi, M.</au><au>Odani, K.</au><au>Mimura, T.</au><au>Abe, M.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 40-ps high electron mobility transistor 4.1 K gate array</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1988-04</date><risdate>1988</risdate><volume>23</volume><issue>2</issue><spage>485</spage><epage>489</epage><pages>485-489</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>A high-electron mobility transistor (HEMT) 4.1 K-gate array has been developed, using a selective dry etching process and a MBE (molecular-beam epitaxy) growth technology. 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subjects	Circuit synthesis Dry etching FETs HEMTs Length measurement Logic circuits Logic design MODFETs Molecular beam epitaxial growth Semiconductor device measurement
title	A 40-ps high electron mobility transistor 4.1 K gate array
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