A 40-ps high electron mobility transistor 4.1 K gate array

A 40-ps high electron mobility transistor 4.1 K gate array

A high-electron mobility transistor (HEMT) 4.1 K-gate array has been developed, using a selective dry etching process and a MBE (molecular-beam epitaxy) growth technology. The circuit design uses direct-coupled FET logic (DCFL). The chip contains 4096 NOR gates, each with a 0.8- mu m gate length, an...

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Veröffentlicht in:IEEE journal of solid-state circuits 1988-04, Vol.23 (2), p.485-489
Hauptverfasser: Kajii, K., Watanabe, Y., Suzuki, M., Hanyu, I., Kosugi, M., Odani, K., Mimura, T., Abe, M.
Format: Artikel
Sprache:eng
Schlagworte:
Circuit synthesis
Dry etching
FETs
HEMTs
Length measurement
Logic circuits
Logic design
MODFETs
Molecular beam epitaxial growth
Semiconductor device measurement
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Zusammenfassung:A high-electron mobility transistor (HEMT) 4.1 K-gate array has been developed, using a selective dry etching process and a MBE (molecular-beam epitaxy) growth technology. The circuit design uses direct-coupled FET logic (DCFL). The chip contains 4096 NOR gates, each with a 0.8- mu m gate length, and measures 6.3 mm*4.8 mm. A basic gate delay of 40 ps has been achieved. A 16*16-bit parallel multiplier, used to test this array, has a multiplication time of 4.1 ns at 300 K, where the power dissipation is 6.2 W.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.1011