Optimal folding of bit sliced stacks

Optimal folding of bit sliced stacks

We develop polynomial time algorithms to optimally fold stacked bit sliced architectures to minimize area subject to height or width constraints. These algorithms may also be applied to folding problems that arise in standard cell and sea-of-gates designs.< >

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Veröffentlicht in:IEEE transactions on computer-aided design of integrated circuits and systems 1993-11, Vol.12 (11), p.1679-1685
Hauptverfasser: Paik, D., Sahni, S.
Format: Artikel
Sprache:eng
Schlagworte:
Algorithm design and analysis
Applied sciences
Circuits
CMOS technology
Design optimization
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Integrated circuits
Polynomials
Routing
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Space technology
Wires
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Beschreibung
Zusammenfassung:We develop polynomial time algorithms to optimally fold stacked bit sliced architectures to minimize area subject to height or width constraints. These algorithms may also be applied to folding problems that arise in standard cell and sea-of-gates designs.< >
ISSN:0278-0070
1937-4151
DOI:10.1109/43.248078