Delay prediction from resistance-capacitance models of general MOS circuits
Most existing techniques for computing the delay in linear resistance-capacitance (RC) networks will yield inaccurate results when applied to MOS transistor circuits, because they do not provide a means for determining the MOSFET's effective channel resistance, which is a function of the capaci...
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| Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 1993-07, Vol.12 (7), p.997-1003 |
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| container_title | IEEE transactions on computer-aided design of integrated circuits and systems |
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| creator | Martin, D. Rumin, N.C. |
| description | Most existing techniques for computing the delay in linear resistance-capacitance (RC) networks will yield inaccurate results when applied to MOS transistor circuits, because they do not provide a means for determining the MOSFET's effective channel resistance, which is a function of the capacitive load. The iterative method, in which the RC network is converted to a tree by node splitting is an exception. An efficient algorithm which takes the above dependence into account by adjusting the resistances in the model within the iterative process of the LM algorithm is presented. It is shown that by focusing on high-capacitance nodes and by distributing the split capacitances on the basis of path conductances, it is possible in many cases to dispense with iteration. For large transistor groups, decomposition into biconnected components is shown to be very effective. Combinations of these techniques have been tested on a large variety of circuits, a representative subset of which is presented.< > |
| doi_str_mv | 10.1109/43.238036 |
| format | Article |
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The iterative method, in which the RC network is converted to a tree by node splitting is an exception. An efficient algorithm which takes the above dependence into account by adjusting the resistances in the model within the iterative process of the LM algorithm is presented. It is shown that by focusing on high-capacitance nodes and by distributing the split capacitances on the basis of path conductances, it is possible in many cases to dispense with iteration. For large transistor groups, decomposition into biconnected components is shown to be very effective. Combinations of these techniques have been tested on a large variety of circuits, a representative subset of which is presented.< ></description><identifier>ISSN: 0278-0070</identifier><identifier>EISSN: 1937-4151</identifier><identifier>DOI: 10.1109/43.238036</identifier><identifier>CODEN: ITCSDI</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Circuit testing ; Computational modeling ; Computer networks ; Delay effects ; Delay lines ; Design. Technologies. Operation analysis. Testing ; Electronics ; Exact sciences and technology ; Integrated circuits ; Microelectronics ; MOSFETs ; Parasitic capacitance ; Predictive models ; Resistors ; Semiconductor electronics. Microelectronics. Optoelectronics. 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The iterative method, in which the RC network is converted to a tree by node splitting is an exception. An efficient algorithm which takes the above dependence into account by adjusting the resistances in the model within the iterative process of the LM algorithm is presented. It is shown that by focusing on high-capacitance nodes and by distributing the split capacitances on the basis of path conductances, it is possible in many cases to dispense with iteration. For large transistor groups, decomposition into biconnected components is shown to be very effective. Combinations of these techniques have been tested on a large variety of circuits, a representative subset of which is presented.< ></description><subject>Applied sciences</subject><subject>Circuit testing</subject><subject>Computational modeling</subject><subject>Computer networks</subject><subject>Delay effects</subject><subject>Delay lines</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Integrated circuits</subject><subject>Microelectronics</subject><subject>MOSFETs</subject><subject>Parasitic capacitance</subject><subject>Predictive models</subject><subject>Resistors</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><issn>0278-0070</issn><issn>1937-4151</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1993</creationdate><recordtype>article</recordtype><recordid>eNqNkD1PwzAQhi0EEuVjYGXygJAYUny2E9sjKp-iqAMwR45zQUb5wk6H_ntSUnXmljvpfe4dHkIugM0BmLmVYs6FZiI7IDMwQiUSUjgkM8aVThhT7JicxPjNGMiUmxl5vcfabmgfsPRu8F1Lq9A1NGD0cbCtw8TZ3jr_d9OmK7GOtKvoF7YYbE3fVu_U-eDWfohn5KiydcTz3T4ln48PH4vnZLl6elncLRMnhBoSi8CA67RgBQhboDK6KMGYUkieglAlQlaCKlCXUIwQV9JxlaI1vKq0keKUXE-9feh-1hiHvPHRYV3bFrt1zLnWGRtt_APk44AewZsJdKGLMWCV98E3NmxyYPnWay5FPnkd2atdqY3O1lUYzfi4fxBKS5ZtscsJ84i4T3cdv-xAfqM</recordid><startdate>19930701</startdate><enddate>19930701</enddate><creator>Martin, D.</creator><creator>Rumin, N.C.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>7TB</scope><scope>8FD</scope><scope>FR3</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><scope>7U5</scope></search><sort><creationdate>19930701</creationdate><title>Delay prediction from resistance-capacitance models of general MOS circuits</title><author>Martin, D. ; Rumin, N.C.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c337t-ae101285b0b13abe798bd199d3425137de16d17be8d1bb0b274c275ea92ff8943</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1993</creationdate><topic>Applied sciences</topic><topic>Circuit testing</topic><topic>Computational modeling</topic><topic>Computer networks</topic><topic>Delay effects</topic><topic>Delay lines</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Integrated circuits</topic><topic>Microelectronics</topic><topic>MOSFETs</topic><topic>Parasitic capacitance</topic><topic>Predictive models</topic><topic>Resistors</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Martin, D.</creatorcontrib><creatorcontrib>Rumin, N.C.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Mechanical & Transportation Engineering Abstracts</collection><collection>Technology Research Database</collection><collection>Engineering Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><collection>Solid State and Superconductivity Abstracts</collection><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Martin, D.</au><au>Rumin, N.C.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Delay prediction from resistance-capacitance models of general MOS circuits</atitle><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle><stitle>TCAD</stitle><date>1993-07-01</date><risdate>1993</risdate><volume>12</volume><issue>7</issue><spage>997</spage><epage>1003</epage><pages>997-1003</pages><issn>0278-0070</issn><eissn>1937-4151</eissn><coden>ITCSDI</coden><abstract>Most existing techniques for computing the delay in linear resistance-capacitance (RC) networks will yield inaccurate results when applied to MOS transistor circuits, because they do not provide a means for determining the MOSFET's effective channel resistance, which is a function of the capacitive load. The iterative method, in which the RC network is converted to a tree by node splitting is an exception. An efficient algorithm which takes the above dependence into account by adjusting the resistances in the model within the iterative process of the LM algorithm is presented. It is shown that by focusing on high-capacitance nodes and by distributing the split capacitances on the basis of path conductances, it is possible in many cases to dispense with iteration. For large transistor groups, decomposition into biconnected components is shown to be very effective. Combinations of these techniques have been tested on a large variety of circuits, a representative subset of which is presented.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/43.238036</doi><tpages>7</tpages></addata></record> |
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| identifier | ISSN: 0278-0070 |
| ispartof | IEEE transactions on computer-aided design of integrated circuits and systems, 1993-07, Vol.12 (7), p.997-1003 |
| issn | 0278-0070 1937-4151 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Circuit testing Computational modeling Computer networks Delay effects Delay lines Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Integrated circuits Microelectronics MOSFETs Parasitic capacitance Predictive models Resistors Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices |
| title | Delay prediction from resistance-capacitance models of general MOS circuits |
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