Delay prediction from resistance-capacitance models of general MOS circuits

Most existing techniques for computing the delay in linear resistance-capacitance (RC) networks will yield inaccurate results when applied to MOS transistor circuits, because they do not provide a means for determining the MOSFET's effective channel resistance, which is a function of the capacitive load. The iterative method, in which the RC network is converted to a tree by node splitting is an exception. An efficient algorithm which takes the above dependence into account by adjusting the resistances in the model within the iterative process of the LM algorithm is presented. It is shown that by focusing on high-capacitance nodes and by distributing the split capacitances on the basis of path conductances, it is possible in many cases to dispense with iteration. For large transistor groups, decomposition into biconnected components is shown to be very effective. Combinations of these techniques have been tested on a large variety of circuits, a representative subset of which is presented.< >