Architecture of a high speed Reed-Solomon decoder

Architecture of a high speed Reed-Solomon decoder

The authors propose an architecture for an error correction circuit suitable for high-rate data decoding of the Reed-Solomon code. It features a multiple-error correction capability of 4 errors or 8 erasures. The operational steps for multiple-error decoding are reduced by a 4-stage pipeline and a s...

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Veröffentlicht in:IEEE transactions on consumer electronics 1994-02, Vol.40 (1), p.75-82
Hauptverfasser: Iwaki, T., Tanaka, T., Yamada, E., Okuda, T., Sasada, T.
Format: Artikel
Sprache:eng
Schlagworte:
Applied sciences
Circuits
Coding, codes
Decoding
Error correction
Error correction codes
Exact sciences and technology
Galois fields
HDTV
High definition video
Information, signal and communications theory
Pipelines
Reed-Solomon codes
Signal and communications theory
Telecommunications and information theory
Video compression
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Beschreibung
Zusammenfassung:The authors propose an architecture for an error correction circuit suitable for high-rate data decoding of the Reed-Solomon code. It features a multiple-error correction capability of 4 errors or 8 erasures. The operational steps for multiple-error decoding are reduced by a 4-stage pipeline and a superscalar processor of a Galois field. The experimental circuit's 16 Mbyte/s rate of data decoding is sufficient for compressed video signals of high-definition as well as those of standard-definition TVs.< >
ISSN:0098-3063
1558-4127
DOI:10.1109/30.273648