Fabrication and total dose testing of a 256 K1 radiation-hardened SRAM

Describes a 256 K*1 radiation-hard SRAM and the process enhancements that resulted in its successful fabrication, and present total-dose-exposure results. Typical measured performance values include an address-activated access time of 36 ns and a write time of 34 ns. Soft-error studies predict the memory cell to be insensitive to single-event upsets, and rail-span collapse simulations estimate transient dose immunity to greater than 4E9 rads(Si)/s. The technology used was a standard 1.0 mu m two-level metal, non-SORT CMOS, radiation-hard process. SORT refers to selective oxidation to reduce topography, a process that uses silicon nitride masking of active device areas during field oxide growth to reduce vertical dimensions. To improve reliability and cosmetic quality, the process has been modified to provide >or=50% metal step coverage at both metal levels. Total-dose measurements have been made up to 1 Mrad(SiO/sub 2/).< >