Improved circuit technique to reduce h/sub fe/ degradation in bipolar output drivers

Improved circuit technique to reduce h/sub fe/ degradation in bipolar output drivers

h/sub fe/ degradation in bipolar transistors caused by reverse V/sub be/ stress decreases the reliability of BiCMOS circuits. In this paper, we present an improved circuit technique to limit reverse V/sub be/, and thus significantly increase BiCMOS reliability. The technique also reduces the base-em...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE transactions on electron devices 1995-03, Vol.42 (3), p.573-574
Hauptverfasser: Kizilyalli, I.C., McAndrew, C.C.
Format: Artikel
Sprache:eng
Schlagworte:
BiCMOS integrated circuits
Bipolar transistors
Circuit simulation
Degradation
Driver circuits
Hafnium
Iron
MOSFETs
Stress
Switching circuits
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:h/sub fe/ degradation in bipolar transistors caused by reverse V/sub be/ stress decreases the reliability of BiCMOS circuits. In this paper, we present an improved circuit technique to limit reverse V/sub be/, and thus significantly increase BiCMOS reliability. The technique also reduces the base-emitter breakdown voltage constraint on BiCMOS technology design.< >
ISSN:0018-9383
1557-9646
DOI:10.1109/16.368058